ADF5612CCCZ datasheet(21/48 Pages) AD

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Data Sheet

ADF5612

THEORY OF OPERATION

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Rev. 0 | 21 of 48

the desired PFD cycles on the LD_COUNT bits (Register 0x029,

Bits[4:0]). Five loop filter time constants can be used as an initial

approximation of the needed number of PFD cycles, as shown in

the following equation:

PFD Cycles = 52 × π × LFBW ×fPFD

where:

LFBW is the loop filter bandwidth

fPFD is the PFD frequency

Table 9. LD_COUNT Programming

LD_COUNT[4:0]

PFD Cycles

131

195

259

387

515

771

1027

1539

2051

3075

4099

6147

8195

12291

16387

24579

32771

Figure 47. Lock Detector Timing, Bleed Current Disabled

Table 10. Lock Detector Timing, Bleed Current Disabled

Region

Absolute Phase

Difference at PFD

Lock Detector State

>tLDWIN

Low

<tLDWIN

Low, counts PFD cycles

Table 10. Lock Detector Timing, Bleed Current Disabled (Continued)

Region

Absolute Phase

Difference at PFD

Lock Detector State

High, greater than or equal to the desired

PFD cycle count

<tLDWIN

High

>tLDWIN

Low (immediately)

When the charge pump bleed current is enabled, a phase offset is

applied to the PFD inputs. This phase offset, tIDEL, is proportional to

the amount of bleed current. Region 3 and Region 4 in Figure 47

and Figure 48 highlight the PFD phase difference the PLL settles

to when the charge pump bleed current is disabled or enabled,

respectively.

Figure 48. Lock Detector Timing, Bleed Current Enabled

For proper operation of the lock detector, the absolute value of tIDEL

must be less than tLDWIN. The user sets the phase difference lock

window time (tLDWIN) for a valid lock condition on the LDWIN_PW

bits (Register 0x029, Bits[7:5]). Configure the LDWIN_PW bits to

1 for integer mode and to 3 for fractional mode. All other bit field

combinations are not applicable.

Table 11. LDWIN_PW Programming

LDWIN_PW [7:5]

Mode of Operation

001

Integer mode, 100MHz maximum PFD

011

Fractional mode, 100MHz maximum PFD, RF ≥ 3.65GHz

MUXOUT

The MUXOUT bits (Register 0x02B, Bits[7:4]) provide the user

with access to various internal nodes. A common application of

the MUXOUT bits is to serve as an extra lock status output or

to debug PLL-related issues during the hardware and software

development stages of a project. The MUXOUT bits and the SDO

pin have a shared function on the SDO Pin (Pin 19). Refer to Table

12 to access the MUXOUT bits on the SDO pin. In 3-wire mode

(SDO_ACTIVE = 0), set EN_MUXOUT (Register 0x2B, Bit 3) to 1

to output the MUXOUT data. In 4-wire mode (SDO_ACTIVE = 1),

set EN_MUXOUT to 0 to allow SPI data to be read from the device

during a SPI read operation. The CMOS_OV bit (Register 0x035,

Bit 5) determines if the logic high level for the SDO or SDIO pins is

3.3V or 1.8V. See Table 12 for the different SDO pin configurations.

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