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TMP86CS28FG Datasheet(PDF) 48 Page - Toshiba Semiconductor |
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TMP86CS28FG Datasheet(HTML) 48 Page - Toshiba Semiconductor |
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48 / 230 page  Page 38 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86CS28FG Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3. Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on inter- rupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be exe- cuted before setting IMF="1". Note 3: Do not clear IL with read-modify-write instructions such as bit operations. Note 1: *: Don’t care Note 2: Do not set IMF and the interrupt enable flag (EF15 to EF4) to “1” at the same time. Note 3: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on inter- rupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be exe- cuted before setting IMF="1". Interrupt Latches (Initial value: **0*0000 000000**) ILH,ILL (003DH, 003CH) 15 14 13 12 11 10 9876543210 −− IL13 − IL11 IL10 IL9 IL8 IL7 IL6 IL5 IL4 IL3 IL2 ILH (003DH) ILL (003CH) (Initial value: **000000 0000****) ILD,ILE (002FH, 002EH) 15 14 13 12 11 10 9876543210 −− IL29 IL28 IL27 IL26 IL25 IL24 IL23 IL22 IL21 IL20 −−−− ILD (002FH) ILE (002EH) IL30 to IL2 Interrupt latches at RD 0: No interrupt request 1: Interrupt request at WR 0: Clears the interrupt request 1: (Interrupt latch is not set.) R/W Interrupt Enable Registers (Initial value: **0*0000 0000***0) EIRH,EIRL (003BH, 003AH) 15 14 13 12 11 10 9876 54321 0 −− EF13 − EF11 EF10 EF9 EF8 EF7 EF6 EF5 EF4 IMF EIRH (003BH) EIRL (003AH) (Initial value: **000000 0000****) EIRD,EIRE (002DH, 002CH) 15 14 13 12 11 10 9876 54321 0 −− EF29 EF28 EF27 EF26 EF25 EF24 EF23 EF22 EF21 EF20 − −−− EIRD (002DH) EIRE (002CH) EF30 to EF4 Individual-interrupt enable flag (Specified for each bit) 0: 1: Disables the acceptance of each maskable interrupt. Enables the acceptance of each maskable interrupt. R/W IMF Interrupt master enable flag 0: 1: Disables the acceptance of all maskable interrupts Enables the acceptance of all maskable interrupts |
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