TMP86CS44UG datasheet(126/172 Pages) TOSHIBA

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Page 116

11. Synchronous Serial Interface (SIO)

11.3 Function

TMP86CS44UG

Figure 11-9 Example of Transmit Error Processingme

11.3.3.2 Receive mode

The receive mode is selected by writing “01B” to SIOCR<SIOM>.

(1) Starting the receive operation

Receive mode is selected by setting “01” to SIOCR1<SIOM>. Serial clock is selected by using

SIOCR1<SCK>. Transfer direction is selected by using SIOCR1<SIODIR>.

After SIOCR1<SIOS> is set to “1”, SIOSR<SIOF> is set synchronously to “1” the falling edge of

SCK

pin.

Synchronizing with the SCK pin's rising edge, the data is received sequentially from SI pin with the

direction of the bit specified by SBIDIR<SIODIR>.

SIOSR<SEF> is kept in high level, between the first clock falling edge of SCK pin and eighth

clock falling edge.

When 8-bit data is received, the data is transferred to SIORDB from shift register. INTSIO inter-

rupt request is generated and SIOSR<RXF> is set to “1”

Note: In internal clock operation, when the SIOCR1<SIOS> is set to "1", the serial clock is generated

from SCK pin after maximum 1-cycle of serial clock frequency.

(2) During the receive operation

The SIOSR<RXF> is cleared to “0” by reading a data from SIORDB.

In the internal clock operation, the serial clock stops to “H” level by an automatic-wait function

when the all of the 8-bit data has been received. Automatic-wait function is released by reading a

received data from SIORDB. Then, receive operation is restarted after maximum 1-cycle of serial

clock.

In external clock operation, after SIOSR<RXF> is set to “1”, the received data must be read from

SIORDB, before the next data shift-in operation is finished.

Writing transmit

data B

Writing transmit

data A

Unknown

A7 A6

A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0

Start shift

operation

Start shift

operation

Start shift

operation

SIOCR1<SIOS>

SIOSR<SIOF>

SIOSR<SEF>

SCK

SO pin

SIOSR<TXF>

SIOSR<TXERR>

INTSIO

interrupt

request

SIOTDB

SIOCR1

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