TMP86CS44UG datasheet(127/172 Pages) TOSHIBA

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Page 117

TMP86CS44UG

If received data is not read out from SIORDB receive error occurs immediately after shift opera-

tion is finished. Then INTSIO interrupt request is generated after SIOSR<RXERR> is set to “1”.

(3) Stopping the receive operation

There are two ways for stopping the receive operation.

• The way of clearing SIOCR1<SIOS>.

When SIOCR1<SIOS> is cleared to “0”, receive operation is stopped after all of the data is

finished to receive. When receive operation is finished, SIOSR<SIOF> is cleared to “0”.

In external clock operation, SIOCR1<SIOS> must be cleared to “0” before SIOSR<SEF> is

set to “1” by starting the next shift operation.

• The way of setting SIOCR1<SIOINH>.

Receive operation is stopped immediately after SIOCR1<SIOINH> is set to “1”. In this case,

SIOCR1<SIOS>, SIOSR register, SIORDB register and SIOTDB register are initialized.

Figure 11-10 Example of Internal Clock and MSB Receive Mode

A6 A5 A4 A3 A2 A1

B7 B6 B5 B4 B3 B2 B1

C6 C5 C4 C3 C2 C1 C0

Automatic wait

Start shift

operation

Start shift

operation

Start shift

operation

Writing transmit

data A

Writing transmit

data B

Clearing SIOS

Writing transmit

data C

SIOCR1<SIOS>

SIOSR<SIOF>

SIOSR<SEF>

SCK

SI pin

SIOSR<RXF>

INTSIO

interrupt

request

SIORDB

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