TMP86FS23UG datasheet(196/252 Pages) TOSHIBA

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Page 184

17. Multiply-Accumulate (MAC) Unit

17.7 Example of Software Processing

TMP86FS23UG

WA, (RAM_Multiplier

β)

6 cycles/3

µs

(MPLDRL), WA

; Multiplier register

6 cycles/3

µs

WA, (RAM_Multiplicand Z)

6 cycles/3

µs

(MPCDRL), WA

; Multiplicand register

6 cycles/3

µs

; The first calculation is

already completed.

Thus, the next data

can be written.

WA, (RAM_Multiplier y)

6 cycles/3

µs

(MPLDRL), WA

; Multiplier register

6 cycles/3

µs

WA, (RAM_Multiplicand Z)

6 cycles/3

µs

(MPCDRL), WA

; Multiplicand register

6 cycles/3

µs

NOP

; Wait three machine cycles

or longer.

NOP

; (Note 2)

NOP

WA, (RCALDR1)

; Low-order part of the

result register

6 cycles/3

µs

(RAM_Low-order part of

result X), WA

6 cycles/3

µs

WA, (RCALDR3)

; High-order part of the

result register

6 cycles/3

µs

(RAM_High-order part of

result X), WA

6 cycles/3

µs

(Enables interrupts.)

Processing time

51 ms

6 cycles/3

µs

RET

6 cycles/3

µs

Total processing time

µs

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