Electronic Components Datasheet Search
  English  ▼

X  

USB3290 Datasheet(PDF) 24 Page - SMSC Corporation

Part # USB3290
Description  Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface
PDF  46 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

USB3290 Datasheet(HTML) 24 Page - SMSC Corporation

Back Button USB3290 Datasheet HTML 20Page - SMSC Corporation USB3290 Datasheet HTML 21Page - SMSC Corporation USB3290 Datasheet HTML 22Page - SMSC Corporation USB3290 Datasheet HTML 23Page - SMSC Corporation USB3290 Datasheet HTML 24Page - SMSC Corporation USB3290 Datasheet HTML 25Page - SMSC Corporation USB3290 Datasheet HTML 26Page - SMSC Corporation USB3290 Datasheet HTML 27Page - SMSC Corporation USB3290 Datasheet HTML 28Page - SMSC Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 24 / 46 page
background image
Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface
Datasheet
Revision 1.5 (11-02-07)
24
SMSC USB3290
DATASHEET
When the EOP is detected the state machine will enter the Strip EOP state and negate RXACTIVE
and RXVALID. After the EOP has been stripped the Receive State Machine will reenter the RX Wait
state and begin looking for the next packet.
The behavior of the Receive State Machine is described below:
RXACTIVE and RXREADY are sampled on the rising edge of CLKOUT.
In the RX Wait state the receiver is always looking for SYNC.
The USB3290 asserts RXACTIVE when SYNC is detected (Strip SYNC state).
The USB3290 negates RXACTIVE when an EOP is detected and the elasticity buffer is empty
(Strip EOP state).
When RXACTIVE is asserted, RXVALID will be asserted if the RX Holding Register is full.
RXVALID will be negated if the RX Holding Register was not loaded during the previous byte time.
This will occur if 8 stuffed bits have been accumulated.
The SIE must be ready to consume a data byte if RXACTIVE and RXVALID are asserted (RX Data
state).
Figure 7.5 shows the timing relationship between the received data (DP/DM), RXVALID,
RXACTIVE, RXERROR and DATA signals.
Notes:
The USB 2.0 Transceiver does NOT decode Packet ID's (PIDs). They are passed to the SIE for
decoding.
Figure 7.5, Figure 7.6 and Figure 7.7 are timing examples of a HS/FS PHY when it is in HS mode.
When a HS/FS PHY is in FS Mode there are approximately 40 CLKOUT cycles every byte time.
The Receive State Machine assumes that the SIE captures the data on the DATA bus if RXACTIVE
and RXVALID are asserted. In FS mode, RXVALID will only be asserted for one CLKOUT per byte
time.
In Figure 7.5, Figure 7.6 and Figure 7.7 the SYNC pattern on DP/DM is shown as one byte long.
The SYNC pattern received by a device can vary in length. These figures assume that all but the
last 12 bits have been consumed by the hubs between the device and the host controller.
Figure 7.5 Receive Timing for a Handshake Packet (no CRC)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com