3

Cortex-M3 Components

Processor

The Cortex-M3 processor features a low gate count processor core with low latency

interrupt processing that has:

A subset of the Thumb instruction set, defined in the Armv7-M architecture

Banked Stack Pointer (SP)

Hardware divide instructions, SDIV and UDIV

Handler and Thread modes

Thumb and Debug states

Support for interruptible-continued instructions LDM, STM, PUSH, and POP

for low interrupt latency

Automatic processor state saving and restoration for low latency Interrupt Service

Routine (ISR) entry and exit

Support for Armv6 big-endian byte-invariant or little-endian accesses

Support for Armv6 unaligned accesses

Block Diagram

Figure 2: Cortex-M3 processor components