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Optional Instrumentation Trace Macrocell (ITM) for support of printf style debugging

Optional Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer (TPA),

including Single Wire Output (SWO) mode

Optional Embedded Trace Macrocell (ETM) for instruction trace

ETM interface

The ETM interface enables simple connection of an ETM to the processor. It provides a

channel for instruction trace to the ETM.

AHB Trace Macrocell interface

The AHB Trace Macrocell (HTM) interface enables a simple connection of the AHB

trace macrocell to the processor. It provides a channel for the data trace to the HTM.

Your implementation must include this interface to use the HTM interface. You must

set TRCENA to 1 in the Debug Exception and Monitor Control Register (DEMCR) before

you enable the HTM to enable the HTM port to supply trace data.

Bus interfaces

Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, DCode,

and System bus interfaces

Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB) interface

Bit-band support that includes atomic bit-band write and read operations

Memory access alignment

Write buffer for buffering of write data

Exclusive access transfers for multiprocessor systems

Debug port AHB-AP interface

The processor contains an Advanced High-performance Bus Access Port (AHB-AP) interface

for debug accesses. An external Debug Port (DP) component accesses this interface.

The Cortex-M3 system supports three possible DP implementations:

Serial Wire JTAG Debug Port (SWJ-DP)

— The SWJ-DP is a standard CoreSight debug port that combines JTAG-DP

and Serial Wire Debug Port (SW-DP).

SW-DP

— This provides a two-pin interface to the AHB-AP port.

No DP present

— If no debug functionality is present within the processor, a DP is not required.

The two DP implementations provide different mechanisms for debug access to the

processor. Your implementation must contain only one of these components.