AX88796BLF datasheet(3/82 Pages) ASIX

3 / 82 page

ASIX ELECTRONICS CORPORATION

AX88796BLF / AX88796BLI

FIGURES

FIG - 1 AX88796B BLOCK DIAGRAM.................................................................................................................................4

FIG - 2 AX88796B PIN OUT DIAGRAM...............................................................................................................................5

FIG - 3 INTERNAL SRAM MAP ..........................................................................................................................................11

FIG - 4 RECEIVE BUFFER RING..........................................................................................................................................15

FIG - 5 RECEIVE BUFFER RING AT INITIALIZATION...........................................................................................................16

FIG - 6 TX / RX FLOW CONTROL ......................................................................................................................................26

FIG - 7 EEPROM CONNECTIONS.......................................................................................................................................28

FIG - 8 PME AND IRQ SIGNAL GENERATION.....................................................................................................................29

FIG - 9 SMI CONNECTIONS................................................................................................................................................61

TABLES

TAB - 1 LOCAL CPU BUS INTERFACE SIGNALS GROUP ........................................................................................................7

TAB - 2 10/100MBPS TWISTED-PAIR INTERFACES PINS GROUP ...........................................................................................7

TAB - 3 BUILT-IN PHY LED INDICATOR PINS GROUP .........................................................................................................7

TAB - 4 EEPROM BUS INTERFACE SIGNALS GROUP............................................................................................................7

TAB - 5 MISCELLANEOUS PINS GROUP .................................................................................................................................8

TAB - 6 EEPROM DATA FORMAT EXAMPLE .......................................................................................................................9

TAB - 7 CSR ADDRESS MAPPING .....................................................................................................................................10

TAB - 8 LOCAL MEMORY MAPPING ..................................................................................................................................10

TAB - 9 INTERNAL SRAM MAP 00H ~ 1FH .....................................................................................................................10

TAB - 10 INTERNAL SRAM MAP 0400H ~ 040FH ...........................................................................................................10

TAB - 11 BYTE LANE MAPPING ........................................................................................................................................27

TAB - 12 POWER MANAGEMENT STATUSES ......................................................................................................................28

TAB - 13 PAGE 0 OF MAC CORE REGISTERS MAPPING ....................................................................................................31

TAB - 14 PAGE 1 OF MAC CORE REGISTERS MAPPING ....................................................................................................32

TAB - 15 PAGE 2 OF MAC CORE REGISTERS MAPPING ....................................................................................................33

TAB - 16 PAGE 3 OF MAC CORE REGISTERS MAPPING ....................................................................................................34

TAB - 17 THE EMBEDDED PHY REGISTERS ......................................................................................................................53

TAB - 18 SMI MANAGEMENT FRAME FORMAT.................................................................................................................61

TAB - 19 MII MANAGEMENT FRAMES- FIELD DESCRIPTION.............................................................................................61

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