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AX88796BLF Datasheet(PDF) 9 Page - ASIX Electronics Corporation |
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AX88796BLF Datasheet(HTML) 9 Page - ASIX Electronics Corporation |
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9 / 82 page  ASIX ELECTRONICS CORPORATION 9 AX88796BLF / AX88796BLI 3.0 Memory and CSR Mapping 1. EEPROM Memory Mapping 2. CSR Mapping 3. Local Memory Mapping 3.1 EEPROM Memory Mapping EEPROM interface can access via CSR offset 14h SMI/EEPROM registers when auto load operation completed. The content of EEPROM data will be auto-loaded to internal memory from 0000h to 001Fh and from 0400h to 040Fh automatically when hardware reset. It is similar to NE2000 PROM store Ethernet address. The real MAC address must configured by PAR0 ~ PAR5 (CR page1 offset1 ~ offset6). The auto-loader only write to internal SRAM not write to PAR0 ~ PAR5. An example as below, if the desired Ethernet physical address is 10-32-54-76-98-BA It is a programmed EEPROM if auto-load value is 5AA5h from EEPROM address 0h. After hardware reset the EEPROM loader will read first word and check pattern 5AA5h. If the first word value not equal to 5AA5h then the EEPROM loader proclaimed that no external EEPROM or external EEPROM is a non-programmed EEPROM. Addr Bits D[15:8] D[7:0] Description 5h [15:0] BAh 98h MAC address 6 th, 5th 4h [15:0] 76h 54h MAC address 4 th, 3rd 3h [15:0] 32h 10h MAC address 2 nd, 1st (multicast bit is 1st of bit_0) [15:11] No define Always zero Configure internal PHY in different ways, such as 10BASE_T half-duplex mode. If EEPROM auto loader not found 5AA5h pattern in first word then internal PHY will be not been manual configuration. (Default is Auto-negotiation enable with all capabilities) [10:8] Function 000 Auto-negotiation enable with all capabilities 001 Auto-negotiation with 100BASE-TX FDX / HDX ability 010 Auto-negotiation with 10BASE-T FDX / HDX ability 011 Reserved 100 Manual selection of 100BASE-TX FDX 101 Manual selection of 100BASE-TX HDX 110 Manual selection of 10BASE-T FDX [10:8] PHY_CONFIG 111 Manual selection of 10BASE-T HDX [7:6] No define Always zero [5] IRQ_TYPE_EEP This bit will logic OR with BTCR (15h) bit-5 and will been clear when host write BTCR. (Offset 15h) [4] IRQ_POL_EEP This bit will logic OR with BTCR (15h) bit-4 and will been clear when host write BTCR. (Offset 15h) [3] No define Always zero [2] NE2000_PROM When set, AX88796B internal memory map of 1Ch ~ 1Fh will be configured to 57h. An ASCII code “W”. Otherwise configured to 42h. An ASCII code “B”. 2h [1:0] No define Always zero 1h [15:0] 00h 06h Indicates the total of word counts for auto loading 0h [15:0] 5Ah A5h Programmed pattern Tab - 6 EEPROM data format example |
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