Data Sheet

AD7767

SPECIFICATIONS

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Rev. D | 7 of 23

1 t2 and t3 allow a ~90% to 10% duty cycle to be used for the MCLK input, where the minimum is 10% for the clock high time and 90% for MCLK low time. The maximum

MCLK frequency is 1.024 MHz.

2 n = 1 for AD7767, n = 2 for the AD7767-1, n = 4 for the AD7767-2.

TIMING DIAGRAMS

Figure 2. DRDY vs. MCLK Timing Diagram, n = 1 for AD7767 (Decimate by 8), n = 2 for AD7767-1 (Decimate by 16), n = 4 for AD7767-2 (Decimate by 32)

Figure 3. Serial Timing Diagram, Reading Data Using CS

Figure 4. Serial Timing Diagram, Reading Data Setting CS Logic Low

Figure 5. Reset, Synchronization, and Power-Down Timing (For More Information, See the Power-Down, Reset, and Synchronization Section)