Data Sheet

ADF41510

SPECIFICATIONS

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Rev. A | 4 of 29

Table 1. Specifications (Continued)

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Output High Current, Output Low Current

(IOH, IOL)

500

µA

POWER SUPPLIES

AVDD1, AVDD2, AVDD3, AVDD4, AVDD5, VP

3.135

3.3

3.465

V

IDD11

1.9

2.2

mA

Current drawn by AVDD1

IDD21

60.5

78

mA

Current drawn by AVDD2

IDD31

2.6

3

mA

Current drawn by AVDD3

IDD41

1.3

1.6

mA

Current drawn by AVDD4

IDD51

15

17

mA

Current drawn by AVDD5

IP1

5.7

6.2

mA

Current drawn by VP

ITOTAL1

87

108

mA

Total current drawn by AVDDx and VP

Power-Down Mode

100

µA

TA = 25°C, CE is low, total of all rails

NOISE CHARACTERISTICS

Normalized Phase Noise Floor (PNSYNTH)

In Integer-N Mode2

−235

dBc/Hz

PLL loop bandwidth (BW) = 1 MHz (Integer-N mode)

In Fractional-N Mode3

−231

dBc/Hz

PLL loop BW = 1 MHz (Fractional-N mode)

Normalized 1∕f Noise (PN1_f)3

−128

dBc/Hz

10 kHz offset, normalized to 1 GHz

SPURIOUS SIGNALS

Reference Spurious

−90

dBc

At reference = 100 MHz, PLL loop BW = 40 kHz

PFD Spurious

−87

dBc

At PFD = 50 MHz, PLL loop BW = 40 kHz

In-Band Integer Boundary Spurious

−45

dBc

10 kHz offset, PLL loop BW = 250 kHz

1 Typ is at TA = 25°C, max is at TA = across Temperature, AVDDx = 3.3 V (where x = 1, 2, 3, or 4), fRFIN = 10.001 GHz, REFIN = 100 MHz, PFD frequency input (fPFD) = 100

MHz.

2 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value)

and 10 log fPFD. PNSYNTH is the total phase noise measured at the VCO output (PNTOT) − 10 log fPFD − 20 log N.

3 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF output frequency,

fRF, and at a frequency offset, f, is given by phase noise (PN) = P1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are

modeled in ADIsimPLL.

TIMING CHARACTERISTICS

AVDDx = AVDD1 = AVDD2 = AVDD3 = AVDD4 = AVDD5 = VP = 3.3 V ± 5%, GND = 0 V, RSET = 1.8 kΩ, dBm referred to 50 Ω, TA = TMIN (−40°C) to

TMAX (+105°C), unless otherwise noted.

Table 2. Read and Write Timing

Parameter

Limit at TMIN to TMAX

Unit

Test Conditions/Comments

t1

10

ns min

LE setup time

t2

5

ns min

DATA to CLK setup time

t3

5

ns min

DATA to CLK hold time

t4

12.5

ns min

CLK high duration

t5

12.5

ns min

CLK low duration

t6

5

ns min

CLK to LE setup time

t7

10

ns min

LE pulse width

t8

20

ns max

LE setup time to MUXOUT when MUXOUT is configured as SPI output

t9

20

ns max

CLK setup time to MUXOUT when MUXOUT is configured as SPI output