Data Sheet

ADF41510

10 GHz, Integer-N/Fractional-N PLL Synthesizer

Rev. A

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FEATURES

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1 GHz to 10 GHz bandwidth

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Ultra-low noise phase locked loop (PLL)

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Integer-N = −235 dBc/Hz, fractional-N = −231 dBc/Hz

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High maximum phase frequency detector (PFD) frequency

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Integer-N = 250 MHz, fractional-N = 125 MHz

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25-bit fixed/49-bit variable fractional modulus mode

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Single-ended reference input

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3.3 V power supply, 3.3 V charge pump

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Integrated 1.8 V logic capability

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Phase resync

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Programmable charge pump currents: 16× range

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Digital lock detect (DLD)

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3-wire serial interface with register readback option

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Hardware and software power-down mode

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Operating range: −40°C to +105°C

APPLICATIONS

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Test equipment and instrumentation

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Wireless infrastructure

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Microwave point-to-point and multipoint radios

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Very small aperture terminal (VSAT) radios

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Aerospace and defense

GENERAL DESCRIPTION

The ADF41510 is an ultra-low noise frequency synthesizer that can

be used to implement local oscillators (LOs) as high as 10 GHz in

the upconversion and downconversion sections of wireless receiv-

ers and transmitters.

The ADF41510 is designed on a high-performance silicon germa-

nium (SiGe), bipolar complementary metal-oxide semiconductor

(BiCMOS) process, achieving a normalized phase noise floor

of −235 dBc/Hz. The PFD operates up to 250 MHz (integer-N

mode)/125 MHz (fractional-N mode) for improved phase noise and

spur performance. The variable modulus, ∑-Δ modulator, allows

extremely fine resolution when using a 49-bit divide value. The

ADF41510 can be used as an integer-N PLL, or it can be used as a

fractional-N PLL with either a fixed modulus for subhertz frequency

resolution or variable modulus for subhertz exact frequency resolu-

tion.

A complete PLL is implemented when the synthesizer is used with

an external loop filter and voltage-controlled oscillator (VCO). The

10 GHz bandwidth eliminates the need for a frequency doubler or

divider stage, simplifying system architecture and reducing cost.

The ADF41510 is packaged in a compact, 24-lead, 4 mm × 4 mm

LFCSP.

FUNCTIONAL BLOCK DIAGRAM

Figure 1. Functional Block Diagram