CDC1104

SCAS921

– SEPTEMBER 2011

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

PIN FUNCTIONS

NO.

NAME

TYPE(1)

DESCRIPTION

1

S2

I

Output clock select. Refer to Output Clock Selection Table

2

S1

I

Output clock select. Refer to Output Clock Selection Table

3

CLKIN

I

Clock Input

4

S3

I

Output clock select. Refer to Output Clock Selection Table

5

GND

P

Ground

6

S4

I

Not internally connected

7

CLKOUT3

O

Buffered CLK Output. Refer to Output Clock Selection Table

8

CLKOUT4

O

Buffered CLK Output. Refer to Output Clock Selection Table

9

OE

I

Chip Enable

10

CLKOUT2

O

Buffered CLK Output. Refer to Output Clock Selection Table

11

VDD

P

Inverted output. No counter delay

12

CLKOUT1

O

Buffered CLK Output. Refer to Output Clock Selection Table

(1)

G = Ground, I = Input, O = Output, P = Power

TRUTH TABLE

INPUTS

OUTPUTS

OE

CLKIN

S4

S3

S2

S1

CLKOUT4

CLKOUT3

CLKOUT2

CLKOUT1

0

CLK

X

X

X

X

L

L

L

L

1

CLK

0

0

0

0

L

L

L

L

1

CLK

0

0

0

1

CLK\

CLK\

CLK\

CLK

1

CLK

0

0

1

0

CLK\

CLK\

CLK

CLK\

1

CLK

0

0

1

1

CLK\

CLK\

CLK

CLK

1

CLK

0

1

0

0

CLK\

CLK

CLK\

CLK\

1

CLK

0

1

0

1

CLK\

CLK

CLK\

CLK

1

CLK

0

1

1

0

CLK\

CLK

CLK

CLK\

1

CLK

0

1

1

1

CLK\

CLK

CLK

CLK

1

CLK

1

0

0

0

CLK

CLK\

CLK\

CLK\

1

CLK

1

0

0

1

CLK

CLK\

CLK\

CLK

1

CLK

1

0

1

0

CLK

CLK\

CLK

CLK\

1

CLK

1

0

1

1

CLK

CLK\

CLK

CLK

1

CLK

1

1

0

0

CLK

CLK

CLK\

CLK\

1

CLK

1

1

0

1

CLK

CLK

CLK\

CLK

1

CLK

1

1

1

0

CLK

CLK

CLK

CLK\

1

CLK

1

1

1

1

CLK

CLK

CLK

CLK

2

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