OE

CLKIN

CLKOUT1

CLKOUT2

CLKOUT3

CLKOUT4

S4=0, S3=0, S2=1, S1=1

S4=1, S3=1, S2=1, S1=0

Change Area

S4=1, S3=1, S2=0, S1=1

Change Area

OE

CLKIN

CLKOUT

Sx in any stable state

Valid Clock according to Sx

10 S (min)

OE

CLKIN

CLKOUT

Sx in any stable state

Valid Clock according to Sx

10 S (min)

CDC1104

www.ti.com

SCAS921

– SEPTEMBER 2011

Timing Diagram For Glitch Free Operation

Transition of outputs from any state to any other state

NOTE: Transition to new state will happen after a latency of one output clock cycle after completing the present output clock

cycle. Transition to new state will happen after a latency of up to 3 input clock cycles excluding the input cycle where

the transition has occurred.

Power Up

NOTE: Transition to new state will happen after a latency of 2 input clock cycles excluding the input cycle where the

transition has occurred.

OE Operation

NOTE: Transition to new state will happen after a latency of 2 input clock cycles excluding the input cycle where the

transition has occurred.

Copyright

© 2011, Texas Instruments Incorporated

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