A–1

Appendix A

Programmable Register Set

Bits D12–D8 in a secondary serial communication comprise the address of the register that is written with data carried

in bits D7–D0. D13 determines a read or write cycle to the addressed register. When low (0), a write cycle is selected.

The following table shows the register map.

Table A–1. Register Map

REGISTER NO.

D15

D14

D13

D12

D11

D10

D9

D8

REGISTER NAME

1

0

0

R/W

0

0

0

0

1

Control 1

2

0

0

R/W

0

0

0

1

0

Control 2

Table A–2. Control Register 1

D7

D6

D5

D4

D3

D2

D1

D0

DESCRIPTION

1















Software reset asserted

0















Software reset not asserted



1













S/W power down enabled



0













S/W power down disabled





1











Digital loopback asserted





0











Digital loopback not asserted







1









Analog loopback asserted







0









Analog loopback not asserted









1







Select data_in PGA for monitor amp input









0







Select DAC output for monitor amp input











1

0

1

Monitor amp PGA gain = 12 dB











1

0

0

Monitor amp PGA gain = 9 dB











0

1

1

Monitor amp PGA gain = 6 dB











0

1

0

Monitor amp PGA gain = 3 dB











0

0

1

Monitor amp PGA gain = 0 dB











0

0

0

Monitor amp PGA gain = mute

Default value: 00000000