SN54HC652, SN74HC652

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCLS151E – DECEMBER 1982 – REVISED MARCH 2003

2

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

description/ordering information (continued)

Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at

the appropriate clock (CLKAB or CLKBA) terminals, regardless of the select- or output-control terminals. When

SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type

flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input.

When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains

at its last state.

To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a

pullup resistor, and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor

is determined by the current-sinking/current-sourcing capability of the driver.

FUNCTION TABLE

INPUTS

DATA I/O†

OPERATION OR FUNCTION

OEAB

OEBA

CLKAB

CLKBA

SAB

SBA

A1–A8

B1–B8

OPERATION OR FUNCTION

L

H

H or L

H or L

X

X

Input

Input

Isolation

L

H

↑↑

X

X

Input

Input

Store A and B data

X

H

↑

H or L

X

X

Input

Unspecified‡

Store A, hold B

H

H

↑↑

X‡

X

Input

Output

Store A in both registers

L

X

H or L

↑

X

X

Unspecified‡

Input

Hold A, store B

L

L

↑↑

XX‡

Output

Input

Store B in both registers

L

L

X

X

X

L

Output

Input

Real-time B data to A bus

L

L

X

H or L

X

H

Output

Input

Stored B data to A bus

H

H

X

X

L

X

Input

Output

Real-time A data to B bus

H

H

H or L

X

H

X

Input

Output

Stored A data to B bus

H

L

H or L

H or L

H

H

Output

Output

Stored A data to B bus and

stored B data to A bus

† The data-output functions are enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always are enabled;

i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs.

‡ Select control = L: clocks can occur simultaneously.

Select control = H: clocks must be staggered to load both registers.