bq2016

GAS GAUGE IC FOR

HIGH DISCHARGE RATES

SLUS475A– JANUARY 2001 – REVISED NOVEMBER 2002

17

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

registers (continued)

DR2–0

The DR2–0 bits represent the present discharge rate of the battery according to the following code:

DISCHARGE RATE INDICATION

DISCHARGE RATE (R)

DR2

DR1

DR0

R

≤ 1C

0

0

0

1C

< R ≤ 3C

0

0

1

3C

< R ≤ 6C

0

1

0

6C

< R ≤ 9C

0

1

1

9C

< R ≤ 12C

1

0

0

R

> 12C

1

0

1

OVLD

The bq2016 set the OVLD bit when it detects that the present discharge rate exceeds the programmed overload

threshold.

Bit = Condition

0

Discharge rate is below the overload threshold.

1

Discharge rate is above the overload threshold.

VPFC (0x07) – VPFC Pin Input Level

VPFC stores the input level at the VPFC programming pin. The voltage at the VPFC (VVPFC) pin is calculated

by

VVPFC (mV) = Vcc × (VPFC/256)

VPROG (0x08) – VPROG Pin Input Level

VPROG stores the input level at the VPROG programming pin. The voltage at the VPROG (VPROG) pin is

calculated by:

VVPROG (mV) = Vcc × (VPROG/256)

CPI (0x09) – Capacity Input Level

CPI stores the number of valid charge actions since the last LMD update.

OCTL (0x0a) – Output Control

OCTL provides a means of testing LED functionality. The register consists of:

7

6

5

4

3

2

1

0

RSVD

RSVD

OCTL5

OCTL4

OCTL3

OCTL2

OCTL1

Enable

When Enable is low, the bq2016 writes the data in OCTL5–1 to the LED5–1 pins. A one in OCTL5–1 turns the

corresponding LED on. This function overrides the LED indication as a representation of capacity.

FULCNT (0x0b) – Full Count Register

FULCNT store the number of times the battery has been charged to full (NAC=LMD) in 16 count increments.

CMDWD (0x0c) – Command Word

The CMDWD register can be used to reset the bq2016 or initiate a VFC offset calibration.

To reset the bq2016, 0x78 must be written to this location. When reset, the bq2016 sets the following values:

NAC = 0

LMD = PFC

CPI = 0

FULCNT = 0

DCR = 0