9

®

DAC811

ADDRESS BUS

A3

A2

A1

A0

OPERATION

0

0

0

0

Load 8 LSB – D/A #1

0

0

0

1

Load 4 MSB – D/A #1

0

0

1

0

Load 8 MSB – D/A #2

0

0

1

1

Load 4 MSB – D/A #2

0

1

0

0

Load 8 MSB – D/A #3

0

1

0

1

Load 4 MSB – D/A #3

0

1

1

0

Load 8 MSB – D/A #4

0

1

1

1

Load 4 MSB – D/A #4

1

X

X

X

Load D/A Latch—All D/A

FIGURE 12. Interfacing Multiple DAC811s to an 8-Bit Bus.

Base

Address

Decoder

WR

A

A

15

4

A

A

A

2

1

0

A

3

74LS138

C

B

A

G

G

G

2A

2B

1

WR

LDAC

N

N

N

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

15

14

13

12

11

10

9

7

3

2

1

4

6

5

CS

DAC811

(4)

C

B

A

WR

LDAC

N

N

N

DAC811

(1)

C

B

A

WR

LDAC

N

N

N

DAC811

(2)

C

B

A

INTERFACING MULTIPLE DAC811s

IN 8-BIT SYSTEMS

Many applications, such as automatic test systems, require

that the outputs of several D/A converters be updated simul-

taneously. The interface shown in Figure 12 uses a 74LS138

decoder to decode a set of eight adjacent addresses, to load

the input latches of four DAC811s. The example shows a

right-justified data format.

A ninth address using A3 causes all DAC811s to be updated

simultaneously. If a particular DAC811 is always loaded

last—for instance, D/A #4—A3 is not needed, thus saving

eight address spaces for other uses. Incorporate A3 into the

base address decoder, remove the inverter, connect the

common LDAC line to NC of D/A #4, and connect D1 of the

74LS138 to +5V.

12- AND 16-BIT MICROCOMPUTER INTERFACE

For this application, the input latch enable lines, NA, NB and

NC, are tied low, causing the latches to be transparent. The

D/A latch, and therefore DAC811, is selected by the address

decoder and strobed by WR.