MPC8358E datasheet(79/96 Pages) FREESCALE

79 / 96 page

MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1

Freescale Semiconductor

Clocking

22.2

Core PLL Configuration

RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300

core clock (core_clk). Table 71 shows the encodings for RCWL[COREPLL]. COREPLL values not listed

in Table 71 should be considered reserved.

High

0010

2 : 1

133

High

0011

3 : 1

100

200

High

0100

4 : 1

133

266

High

0101

5 : 1

166

333

High

0110

6 : 1

200

High

0111

7 : 1

233

High

1000

8 : 1

High

1001

9 : 1

High

1010

10 : 1

High

1011

11 : 1

High

1100

12 : 1

High

1101

13 : 1

High

1110

14 : 1

High

1111

15 : 1

High

0000

16 : 1

CFG_CLKIN_DIV is only used for host mode; CLKIN must be tied low and CFG_CLKIN_DIV must be

pulled down (low) in agent mode.

CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.

Table 71. e300 Core PLL Configuration

RCWL[COREPLL]

core_clk : csb_clk Ratio

VCO divider

0-1

2-5

0000

PLL bypassed

(PLL off,

csb_clk clocks core

directly)

PLL bypassed

(PLL off,

csb_clk clocks core

directly)

0001

01:1

÷2

0001

01:1

÷4

Table 70. CSB Frequency Options (continued)

CFG_CLKIN_DIV

at reset 1

SPMF

csb_clk :

Input Clock

Ratio 2

Input Clock Frequency (MHz)2

16.67

33.33

66.67

csb_clk Frequency (MHz)

MPC8358E Datasheet(PDF) 79 Page - Freescale Semiconductor, Inc

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