ADS1271IPWR datasheet(21/40 Pages) TI2

21 / 40 page

ADS1271

SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007

www.ti.com

POWER-DOWN AND OFFSET CALIBRATION

addition

controlling

synchronization,

the

SYNC/PDWN

pin also serves as the control for

Power-Down mode and offset calibration. To enter this

mode, hold the SYNC/PDWN pin low for at least 219 CLK

periods. While in Power-Down mode, both the analog and

digital circuitry are completely deactivated. The digital

inputs are internally disabled so that is not necessary to

shut down CLK and SCLK. To exit Power-Down mode,

return SYNC/PDWN high on the rising edge of CLK.

The ADS1271 uses a chopper-stabilized modulator to

provide inherently very low offset drift. To further minimize

offset, the ADS1271 automatically performs an offset

self-calibration when exiting Power-Down mode. When

power down completes, the offset self-calibration begins

with

the

inputs

AINP

and

AINN

automatically

disconnected from the signal source and internally shorted

together. There is no need to modify the signal source

applied to the analog inputs during this calibration.

It is critical for the reference voltage to be stable when

exiting Power-Down mode; otherwise, the calibration will

be corrupted.

The offset self-calibration only removes offset errors internal

to the device, not offset errors due to external sources.

NOTE: When an offset self-calibration is performed, the

resulting offset value will vary each time within the

peak-to-peak noise range of the converter. In High-Speed

mode, this is typically 178 LSBs.

The offset calibration value is cleared whenever the device

mode is changed (for example, from High-Speed mode to

High-Resolution mode).

When using the SPI format, DRDY will stay high after

exiting Power-Down mode while the digital filter settles, as

shown in Figure 52.

When using the Frame-Sync format, DOUT will stay low

after exiting Power-Down mode while the digital filter

settles, as shown in Figure 53.

NOTE: In Power-Down mode, the inputs of the ADS1271

must be driven (do not float) and the device drives the

outputs driven to a DC level.

Status

CLK

Converting

Sync

Power Down

Converting

Post−Calibration

Data Ready

Offset Cal and Filter Settling

DRDY

•• •

SYNC/PDWN

tPDWN

tOFS

SYMBOL

tPDWN

pulse width to enter Power−Down mode

219

CLK periods

OFS

Time for offset calibration and filter settling

256

Conversions

(1/f

DATA)

MIN

TYP

MAX

UNITS

DESCRIPTION

SYNC/PDWN

Figure 52. Power-Down Timing for SPI format

SYMBOL

PDWN

pulse width to enter Power−Down mode

219

CLK periods

OFS

Time for offset calibration and filter settling

257

256

Conversions

(1/f

DATA)

MIN

TYP

MAX

UNITS

DESCRIPTION

Status

CLK

FSYNC

DOUT

•••

SYNC/PDWN

OFS

PDWN

Converting

Sync

Power Down

Converting

Post−Calibration Data

Offset Cal and Filter Settling

SYNC/PDWN

Figure 53. Power-Down Timing for Frame-Sync Format

ADS1271IPWR Datasheet(PDF) 21 Page - Texas Instruments

ADS1271IPWR Datasheet(HTML) 21 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL