ADS5287

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SBAS428D – JANUARY 2008 – REVISED JUNE 2012

SERIAL REGISTER MAP

Table 3. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE(1) (2) (3) (4)

ADDRESS

IN HEX

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

NAME

DESCRIPTION

DEFAULT

00

X

RST

Self-clearing software RESET.

Inactive

Channel-specific ADC power-

X

X

X

X

X

X

X

X

PDN_CH<8:1>

Inactive

down mode.

Partial power-down mode (fast

X

PDN_PARTIAL

Inactive

recovery from power-down).

0F

Register mode for complete

X

PDN_COMPLETE

Inactive

power-down (slower recovery).

Configures the PD pin for partial

Complete

X

PDN_PIN_CFG

power-down mode.

power-down

LVDS current drive

X

X

X

ILVDS_LCLK<2:0>

programmability for LCLKN and

3.5mA drive

LCLKP pins.

LVDS current drive

ILVDS_FRAME

11

X

X

X

programmability for ADCLKN and

3.5mA drive

<2:0>

ADCLKP pins.

LVDS current drive

X

X

X

ILVDS_DAT<2:0>

programmability for OUTN and

3.5mA drive

OUTP pins.

Enables internal termination for

Termination

X

EN_LVDS_TERM

LVDS buffers.

disabled

Programmable termination for

Termination

1

X

X

X

TERM_LCLK<2:0>

LCLKN and LCLKP buffers.

disabled

12

TERM_FRAME

Programmable termination for

Termination

1

X

X

X

<2:0>

ADCLKN and ADCLKP buffers.

disabled

Programmable termination for

Termination

1

X

X

X

TERM_DAT<2:0>

OUTN and OUTP buffers.

disabled

Channel-specific, low-frequency

14

X

X

X

X

X

X

X

X

LFNS_CH<8:1>

Inactive

noise suppression mode enable.

INP is

Swaps the polarity of the analog

24

X

X

X

X

X

X

X

X

INVERT_CH<8:1>

positive

input pins electrically.

input

Enables a repeating full-scale

X

0

0

EN_RAMP

Inactive

ramp pattern on the outputs.

Enables the mode wherein the

DUALCUSTOM_

0

X

0

output toggles between two

Inactive

PAT

defined codes.

Enables the mode wherein the

SINGLE_CUSTOM

0

0

X

output is a constant specified

Inactive

25

_PAT

code.

2MSBs for a single custom

BITS_CUSTOM1

pattern (and for the first code of

X

X

Inactive

<9:8>

the dual custom pattern). <9> is

the MSB.

BITS_CUSTOM2

2MSBs for the second code of

X

X

Inactive

<9:8>

the dual custom pattern.

8 lower bits for the single custom

BITS_CUSTOM1

pattern (and for the first code of

26

X

X

X

X

X

X

X

X

Inactive

<7:0>

the dual custom pattern). <0> is

the LSB.

BITS_CUSTOM2

8 lower bits for the second code

27

X

X

X

X

X

X

X

X

Inactive

<7:0>

of the dual custom pattern.

X

X

X

X

GAIN_CH1<3:0>

Programmable gain channel 1.

0dB gain

X

X

X

X

GAIN_CH2<3:0>

Programmable gain channel 2.

0dB gain

2A

X

X

X

X

GAIN_CH3<3:0>

Programmable gain channel 3.

0dB gain

X

X

X

X

GAIN_CH4<3:0>

Programmable gain channel 4.

0dB gain

X

X

X

X

GAIN_CH5<3:0>

Programmable gain channel 5.

0dB gain

X

X

X

X

GAIN_CH6<3:0>

Programmable gain channel 6.

0dB gain

2B

X

X

X

X

GAIN_CH7<3:0>

Programmable gain channel 7.

0dB gain

X

X

X

X

GAIN_CH8<3:0>

Programmable gain channel 8.

0dB gain

(1)

The unused bits in each register (identified as blank table cells) must be programmed as '0'.

(2)

X = Register bit referenced by the corresponding name and description (default is 0).

(3)

Bits marked as '0' should be forced to 0, and bits marked as '1' should be forced to 1 when the particular register is programmed.

(4)

Multiple functions in a register should be programmed in a single write operation.

Copyright © 2008–2012, Texas Instruments Incorporated

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