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ADS8519IBDBR Datasheet(PDF) 7 Page - Texas Instruments

Part # ADS8519IBDBR
Description  16-Bit, 250kSPS, Serial, CMOS, Sampling ANALOG-TO-DIGITAL CONVERTER
PDF  31 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

ADS8519IBDBR Datasheet(HTML) 7 Page - Texas Instruments

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background image
1
2
tsu1
tsu1
CS
R/C
External
DATACLK
CS Set Low, Discontinuous Ext DATACLK
tsu1
tsu1
R/C
CS
External
DATACLK
R/C Set Low, Discontinuous Ext DATACLK
tsu2
tsu2
CS
R/C
tsu3
BUSY
External
DATACLK
CS Set Low, Discontinuous Ext DATACLK
Setup Time, R/C to CS
ADS8519
www.ti.com
SLAS462D – JUNE 2007 – REVISED SEPTEMBER 2010
TIMING REQUIREMENTS, TA = –40°C to +85°C
PARAMETER
MIN
TYP
MAX
UNIT
tw1
Pulse duration, convert
40
ns
td1
Delay time, BUSY from R/C low
6
20
ns
tw2
Pulse duration, BUSY low
2.2
ms
td2
Delay time, BUSY, after end of conversion
5
ns
td3
Delay time, aperture
5
ns
tconv
Conversion time
2.2
ms
tacq
Acquisition time
1.8
ms
tconv + tacq Cycle time
4
ms
td4
Delay time, R/C Low to internal DATACLK output
270
ns
tc1
Cycle time, internal DATACLK
110
ns
td5
Delay time, data valid to internal DATACLK high
15
35
ns
td6
Delay time, data valid after internal DATACLK low
20
35
ns
tc2
Cycle time, external DATACLK
35
ns
tw3
Pulse duration, external DATACLK high
15
ns
tw4
Pulse duration, external DATACLK low
15
ns
tsu1
Setup time, R/C rise/fall to external DATACLK high
15
ns
tsu2
Setup time, R/C transition to CS transition
10
ns
td7
Delay time, SYNC, after external DATACLK high
3
35
ns
td8
Delay time, data valid from external DATACLK high
2
13
ns
td9
Delay time, CS rising edge to external DATACLK rising edge
10
ns
td10
Delay time, previous data available after CS, R/C low
2
ms
tsu3
Setup time, BUSY transition to first external DATACLK
5
ns
td11
Delay time, final external DATACLK to BUSY rising edge
1
ms
tsu4
Setup time, TAG valid
0
ns
th1
Hold time, TAG valid
2
ns
TIMING DIAGRAMS
Figure 1. Critical Timing
Copyright © 2007–2010, Texas Instruments Incorporated
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