SMBus Level 2 Battery Charger

with Remote Sense

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13

Pin Description

PIN

NAME

FUNCTION

1, 12

GND

Analog Ground. Connect directly to the paddle.

2

ACIN

AC Adapter Detect Input. ACIN is the input to an uncommitted comparator.

3

REF

4.096V Voltage Reference. Bypass REF with a 1µF capacitor to GND.

4

CCS

Input Current Regulation Loop-Compensation Point. Connect 0.01µF from CCS to GND.

5

CCI

Output Current Regulation Loop-Compensation Point. Connect 0.01µF from CCI to GND.

6

CCV

Voltage Regulation Loop-Compensation Point. Connect 10k

Ω in series with 0.01µF to GND.

7

DAC

DAC Voltage Output. Bypass with 0.1µF from DAC to GND.

8

IINP

Input Current Monitor Output. IINP sources the current proportional to the current sensed across

CSSP and CSSN. The transconductance from (CSSP - CSSN) to IINP is 3mA/V.

9

SDA

SMBus Data I/O. Open-drain output. Connect an external pullup resistor according to SMBus specifications.

10

SCL

SMBus Clock Input. Connect an external pullup resistor according to SMBus specifications.

11

Logic Circuitry Supply-Voltage Input. Bypass with a 0.1µF capacitor to GND.

13

ACOK

AC Detect Output. This open-drain output is high impedance when ACIN is greater than REF/2. The

ACOK output remains low when the MAX8731A is powered down. Connect a 10k

Ω pullup resistor from

14

BATSEL

Battery Voltage Select Input. Drive BATSEL high to select battery B, or drive BATSEL low to select battery A.

Any change of BATSEL immediately stops charging. Charging begins again in approximately 10ms.

15

FBSA

Remote-Sense Input for the Output Voltage of Battery A. Connect a 100

Ω resistor from FBSA to the

battery connector, and a 10nF capacitor from FBSA to PGND.

16

FBSB

Remote-Sense Input for the Output Voltage of Battery B. Connect a 100

Ω resistor from FBSB to the

battery connector, and a 10nF capacitor from FBSB to PGND.

17

CSIN

Charge Current-Sense Negative Input

18

CSIP

Charge Current-Sense Positive Input. Connect a 10m

Ω current-sense resistor between CSIP and CSIN.

19

PGND

Power Ground

20

DLO

Low-Side Power MOSFET Driver Output. Connect to low-side n-channel MOSFET. DLO drives

between LDO and PGND.

21

LDO

Linear-Regulator Output. LDO is the output of the 5.4V linear regulator supplied from DCIN. LDO also

directly supplies the DLO driver and the BST charge pump. Bypass with a 1µF ceramic capacitor

from LDO to PGND.

22

DCIN

Charger Bias Supply Input. Bypass DCIN with a 0.1µF capacitor to PGND.

23

LX

High-Side Power MOSFET Driver Source Connection. Connect to the source of the high-side n-channel

MOSFET.

24

DHI

High-Side Power MOSFET Driver Output. Connect to the high-side n-channel MOSFET gate.

25

BST

High-Side Power MOSFET Driver Power-Supply Connection. Connect a 0.1µF capacitor from BST to LX.

26

Device Power-Supply Input. Connect to LDO through an RC filter as shown in Figure 1.

27

CSSN

Input Current-Sense Negative Input

28

CSSP

Input Current-Sense Positive Input. Connect a 10m

Ω current-sense resistor between CSSP and CSSN.

—

BP

Backside Paddle. Connect the backside paddle to analog ground.