LD7752GS datasheet(10/17 Pages) LEADTREND

10 / 17 page

LD7752

Leadtrend Technology Corporation

www.leadtrend.com.tw

LD7752-DS-01 June 2013

Adjustable Grouping Frequency and Soft

Start on CT Pin

In order to prevent the acoustic noise from grouping

frequency Fg, adjust the external capacitance of CT pin,

and the soft start time for it according to the below table.

The grouping frequency is limited from 600Hz to

1.80KHz

CCT (nF)

Grouping frequency

Fg (KHz)

Soft start time

Tss (mS)

22nF

1.2~1.8

≈ 3.0

33nF

0.8~1.3

≈ 3.8

47nF

0.6~1.0

≈ 6.0

Internal Slope Compensation

A fundamental issue of current mode control is the

stability problem when its duty-cycle is operated for

more than 50%. To stabilize the control loop, slope

compensation is required in the traditional UC384X

design by injecting the ramp signal from the RT/CT pin

through a coupling capacitor. Well, LD7752 requires

none of it since there

’s a built-in slope compensation

circuit to simplify the external circuit design.

On/Off Control

Pulling COMP pin below 1.6V will disable the gate

output pin of LD7752 immediately. The off mode will be

released soon as the pull-low signal is removed.

Dual-Oscillator Green-Mode Operation

There are various topologies for chips to meet

green-mode or power saving requirements, such as

“burst-mode control”, “skipping-cycle mode”, “variable

off-time control

“…etc. The basic operation theory of all

these approaches intends to reduce the switching

cycles under light-load or no-load condition either by

skipping some switching pulses or reduce the switching

frequency.

With LD proprietary dual-oscillator technique, the

green-mode frequency can be well controlled and

further to avoid the generation of audible noise.

Over

Load

Protection

(OLP)

Auto

Recovery

To protect the circuit from being damaged in over-load,

short

open

loop

condition,

the

LD7752

implemented with smart OLP function. It also features

auto recovery function; see Fig. 11 for the waveform. If

in fault condition, the feedback system will force the

voltage loop toward the saturation and then pull the

voltage high over COMP pin (VCOMP).

When the VCOMP

ramps up over OLP threshold of 4.5V and stays for

longer than the OLP delay time, the protection will be

activated and then turn off the gate output to stop the

switching of power circuit.

A divide-2 counter is implemented to reduce the

average power under OLP behavior. As soon as OLP is

activated, the output will be latched off and the divide-2

counter starts to count the numbers of UVLO(off). The

latch will be released when the 2nd UVLO(off) point is

tripped, then the output will recover to switch again.

With the protection mechanism, it minimizes the

average input power to control the component

’s

temperature and stress within the safe operating area.

VCC

UVLO(on)

UVLO(off)

COMP

OLP

4.5V

OUT

OLP Delay Time

Switching

Non-Switching

OLP trip Level

2nd UVLO(off)

OLP Counter Reset

Fig. 11

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