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LD7752GS Datasheet(PDF) 11 Page - Leadtrend Technology |
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LD7752GS Datasheet(HTML) 11 Page - Leadtrend Technology |
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11 / 17 page ![]() LD7752 11 Leadtrend Technology Corporation www.leadtrend.com.tw LD7752-DS-01 June 2013 OVP (Over Voltage Protection) on Vcc - Auto Recovery The maximum VGS ratings of the power MOSFETs are mostly set at 30V. To prevent the VGS from damage in fault condition, LD7752 is embedded with OVP function on Vcc. Once the Vcc voltage rises above OVP threshold, it shuts down output gate drive circuit simultaneously and disable the switching of the power MOSFET until the next UVLO(on) is reached. The LD7752 possess auto-recoverable Vcc OVP functions. The OVP condition usually comes with open-loop of feedback. Before it ’s released, the Vcc will trip to OVP level and shutdown the output again. The Vcc works in hiccup mode. Fig. 12 shows its operation. Otherwise, soon as the OVP condition is removed, the Vcc level will be resumed and the output will automatically return to the normal operation. VCC UVLO(on) UVLO(off) t OVP Tripped t OUT Switching Switching Non-Switching OVP Level Fig. 12 Pull-Low Resistor on the Gate Pin of MOSFET The LD7752 consists of an anti-floating resistor on the OUT pin to protect the output from abnormally operation or false triggering of MOSFET. Even so, we still recommend adding an external one at the MOSFET gate terminal to provide more protection in case of disconnection of gate resistor RG during power-on. In single-fault condition, as shown in Fig. 13, the resistor R8 can provide a discharge path to avoid the MOSFET from being false-triggered by the current through the gate-to-drain capacitor CGD. Therefore, the MOSFET is always pulled low and placed in the off-state no matter when the gate resistor is disconnected or opened. CS GND LD7752 It is recommended to add an resistor on the power circuit. OUT Rg R8 An internal pull-low resistor is built in here to prevent from floating. Fig. 13 CS GND LD7752 This resistor is to prevent the MOSFET from false triggering by the current through Cgd in case Rg is disconnected. OUT Rg R8 Cgd dt dV Cgd i bulk Vbulk Fig. 14 |
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