SDA

SCL

STOP

A

P

D0

D1

D2

D3

D4

D5

D6

A

R/W

1

1

1

1

0

0

1

START

DATA

SLAVE ADDRESS

D4

D3

D2

1

0

0

1

1

A

D6

D5

D1

D0

P

A

1

1

STOP

START

W

R/

SDA

SCL

LM8342

SLAVE A

SLAVE B

VDD

PULL-UP

RESISTORS

MASTER

LM8342

www.ti.com

SNOSAM0B – NOVEMBER 2005 – REVISED MARCH 2013

Table 1. Pin Descriptions (continued)

Pin name

Function

SCL-S

For in-circuit PCB testing, the LM8342 can use the additional Switched SCL signal (SCL-S) input

for applying the SCL clock signal.

WPN

“Write Protect Not” (Input) has 2 functions:

1. Prohibits programming the EEPROM, when low or left floating (Internal a pull-down resistor is

connected) When WPN is set to a low level, only the volatile register is accessible. If WPN is set

to a high level also the EEPROM is accessible. Actual writing to the EEPROM or the register is

done using the “P-bit” in the serial communication.

2. WPN switches the SCL-S clock line. When WPN is set to a high level SCL-S is connected to

SCL. The operator should turn off the original SCL clock.

WPP

Write Protect Signal (Output). This is the inverted WPN signal.

I

2C SERIAL INTERFACE BUS

The LM8342 supports an I2C compatible communication protocol, which is a bidirectional bus oriented

communication protocol. Any device that sends data on the bus is defined as a transmitter and the receiving

device as a receiver. The I2C compatible communication protocol uses 2 wires: SDA (Serial Data Line) and SCL

(Serial Clock Line). For both lines an external pull-up resistor, connected to the supply voltage, is required. The

device controlling the bus is known as the master, and the device or devices being controlled are the slaves.

Each device has its own specific address. The address of the LM8342 is 9EHEX. The master initiates the

communication and provides the clock. The LM8342 always operates as a slave. A typical system using an I2C

compatible interface bus is given in Figure 25.

Figure 25. System Using an I2C compatible Bus

The LM8342 can be used in an I2C compatible system. All specifications of the LM8342, dealing with the

interface bus, are ensured by design. Except for the bus speed, which is specified in the Electrical

Characteristics table.

KEY ASPECT OF I

2C COMPATIBLE COMMUNICATION

In this section a brief overview is presented, discussing the key aspect of I2C compatible communication.

Figure 26 shows the timing aspects of the I2C compatible serial interface.

Figure 26. Timing Diagram

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