LM2653

SNVS050E – NOVEMBER 1999 – REVISED APRIL 2013

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PCB Layout Considerations

Layout is critical to reduce noises and ensure specified performance. The important guidelines are listed as

follows:

1. Minimize the parasitic inductance in the loop of input capacitors and the internal MOSFETs by connecting the

input capacitors to VIN and PGND pins with short and wide traces. This is important because the rapidly

switching current, together with wiring inductance can generate large voltage spikes that may result in noise

problems.

2. Minimize the trace from the center of the output resistor divider to the FB pin and keep it away from noise

sources to avoid noise pick up. For applications require tight regulation at the output, a dedicated sense

trace (separated from the power trace) is recommended to connect the top of the resistor divider to the

output.

3. If the Schottky diode D1 is used, minimize the traces connecting D1 to SW and PGND pins.

Figure 16. Schematic for the Typical Board Layout

Typical PC Board Layout: (2X Size)

Figure 17. Component Placement Guide

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