SCL

SDA

tHD;STA

tLOW

tHD;DAT

tHIGH

tSU;DAT

tSU;STA

tSU;STO

tf

START

REPEATED

START

STOP

tHD;STA

START

tSP

tBUF

1/fSCL

tVD;DAT

tVD;ACK

30%

70%

30%

70%

MENB

30%

70%

tEN;START

tEN;STOP

tEN;HIGH

LMP91002

www.ti.com

SNIS163B – APRIL 2012 – REVISED OCTOBER 2015

6.7 Timing Characteristics

Unless otherwise specified, all limits ensured for TA = 25°C, VS= (VDD – AGND), VS= 3.3 V and AGND = DGND = 0 V, VREF

= 2.5 V, Internal Zero= 20% VREF. All limits apply at the temperature extremes. Refer to timing diagram in Figure 1

(1).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fSCL

Clock Frequency

At the temperature extremes

10

100

kHz

tLOW

Clock Low Time

At the temperature extremes

4.7

µs

tHIGH

Clock High Time

At the temperature extremes

4

µs

After this period, the first clock pulse is

tHD;STA

Data valid

4

µs

generated at the temperature extremes

Set-up time for a repeated START

tSU;STA

At the temperature extremes

4.7

µs

condition

tHD;DAT

Data hold time(2)

At the temperature extremes

0

ns

tSU;DAT

Data Set-up time

At the temperature extremes

250

ns

IL

≤ 3 mA, CL ≤ 400 pF,

tf

SDA fall time(3)

250

ns

at the temperature extremes

tSU;STO

Set-up time for STOP condition

At the temperature extremes

4

µs

Bus free time between a STOP and

tBUF

At the temperature extremes

4.7

µs

START condition

tVD;DAT

Data valid time

At the temperature extremes

3.45

µs

tVD;ACK

Data valid acknowledge time

At the temperature extremes

3.45

µs

Pulse width of spikes that must be

tSP

At the temperature extremes

50

ns

suppressed by the input filter(3)

t_timeout

SCL and SDA Timeout

At the temperature extremes

25

100

ms

tEN;START

I2C Interface Enabling

At the temperature extremes

600

ns

tEN;STOP

I2C Interface Disabling

At the temperature extremes

600

ns

time between consecutive I2C

tEN;HIGH

At the temperature extremes

600

ns

interface enabling and disabling

(1)

Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very

limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical

tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond

which the device may be permanently degraded, either mechanically or electrically.

(2)

LMP91002 provides an internal 300ns minimum hold time to bridge the undefined region of the falling edge of SCL.

(3)

This parameter is specified by design or characterization.

Figure 1. I2C Interface Timing Diagram

Copyright © 2012–2015, Texas Instruments Incorporated

Submit Documentation Feedback

7

Product Folder Links: LMP91002