68HC05PL4B datasheet(30/98 Pages) FREESCALE

30 / 98 page

GENERAL RELEASE SPECIFICATION

April 30, 1998

INTERRUPTS

MC68HC05PL4

4-6

REV 2.0

4.5

16-BIT TIMER INTERRUPTS

The 16-bit programmable Timer can generate an interrupt whenever the following

events occur:

•

Input capture

•

Output compare

•

Timer counter over o w

Setting the I bit in the condition code register disables Timer interrupts. The con-

trols for these interrupts are in the Timer control register (TCR) located at $0012

and in the status bits are in the Timer status register (TSR) located at $0013.

The 16-bit programmable Timer interrupts can wake up MCU from WAIT Mode.

4.5.1 Input Capture Interrupt

An input capture interrupt occurs if the input capture ag (ICF) becomes set while

the input capture interrupt enable bit (ICIE) is also set. The ICF ag bit is in the

TSR; and the ICIE enable bit is located in the MICSR. The ICF ag bit is cleared

by a read of the TSR with the ICF ag bit is set; and then followed by a read of the

LSB of the input capture register (ICRL) or by reset. The ICIE enable bit is unaf-

fected by reset.

4.5.2 Output Compare Interrupt

An output compare interrupt occurs if the output compare ag (OCF) becomes set

while the output compare interrupt enable bit (OCIE) is also set. The OCF ag bit

is in the TSR and the OCIE enable bit is in the MICSR. The OCF ag bit is cleared

by a read of the TSR with the OCF ag bit set; and then followed by an access to

the LSB of the output compare register (OCRL) or by reset. The OCIE enable bit is

unaffected by reset.

4.5.3 Timer Overﬂow Interrupt

A Timer over ow interrupt occurs if the Timer over ow ag (TOF) becomes set

while the Timer over o w interrupt enable bit (TOIE) is also set. The TOF ag bit is

in the TSR and the TOIE enable bit is in the TCR. The TOF ag bit is cleared b y a

read of the TSR with the TOF ag bit set; and then followed by an access to the

LSB of the timer registers (TMRL) or by reset. The TOIE enable bit is unaffected

by reset.

4.6

8-BIT TIMER INTERRUPT

The 8-bit Timer can generate an interrupt when the Timer8 Counter Register

(T8CNTR) decrements from preset value to zero and the interrupt enable bit is

set. Setting the I bit in the condition code register disables this Timer interrupts.

The control bit for this interrupt and status bit are in the Timer 8 control register

(T8CSR) located at $000D.

The 8-Bit timer interrupt can wake up MCU from WAIT Mode.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

68HC05PL4B Datasheet(PDF) 30 Page - Freescale Semiconductor, Inc

68HC05PL4B Datasheet(HTML) 30 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

Datasheet Download

Link URL