68HC05PL4B datasheet(38/98 Pages) FREESCALE

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GENERAL RELEASE SPECIFICATION

April 30, 1998

RESETS

MC68HC05PL4

5-6

REV 2.0

•

Does not affect the input capture edge bit (IEDG) in the TCR.

•

Does not affect the interrupt ags in the timer status register (TSR).

•

Does not affect the input capture registers (ICRH, ICRL).

•

Does not affect the output compare registers (OCRH, OCRL).

Therefore con gure the por t A pins PA2,PA3 as general I/O function. However the

timer is free running for interrupt process.

5.4.5 Keyboard Interrupt Interface

A reset has the following effects on the Keyboard Interrupt interface:

•

Clears all bits in Keyboard interrupt enable register (KIER) and

Keyboard interrupt disable

•

Clears all bits in Keyboard interrupt ag register (KIFR)

•

Clears all bits in Pull-Up enable register (PUER)

Therefore disables the Keyboard interrupt and leaves the shared port B pins as

general I/O. Any pending interrupt ag is cleared and the K eyboard interrupt is dis-

abled.

5.4.6 6-bit DAC Subsystem

A reset has the following effects on the DAC subsystem:

•

Clears all bits in DAC control Register, hence DAC subsystem is

disabled.

Therefore con gure the por t A pin PA1 as general I/O function.

5.4.7 System Clock Option Subsystem

At reset has the following effects on OSC clock subsystem

•

The internal RC is enabled and oscillating at around 500kHz

•

Internal clock divider selected to divide by 2 for bus frequency

5.4.8 Miscellaneous Subsystem

A P reset has the following effects on IRQ subsystem

•

IRQ is disabled and reset the IRQ selection as negative edge-triggered

and low level-triggered, hence the LED/IRQ pin function as LED output

Therefore also disable the LED driver output, hence the LED/IRQ pin is in high

impedance state.

Freescale Semiconductor, Inc.

For More Information On This Product,

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68HC05PL4B Datasheet(PDF) 38 Page - Freescale Semiconductor, Inc

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