M68HC08 datasheet(40/172 Pages) FREESCALE

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Central Processor Unit (CPU)

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor

4.3.5 Condition Code Register

The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the

instruction just executed. Bits 6 and 5 are set permanently to logic 1. The following paragraphs describe

the functions of the condition code register.

V — Overflow Flag

The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch

instructions BGT, BGE, BLE, and BLT use the overflow flag.

1 = Overflow

0 = No overflow

H — Half-Carry Flag

The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an

add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for

binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and

C flags to determine the appropriate correction factor.

1 = Carry between bits 3 and 4

0 = No carry between bits 3 and 4

I — Interrupt Mask

When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled

when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set

automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched.

1 = Interrupts disabled

0 = Interrupts enabled

NOTE

To maintain M6805 Family compatibility, the upper byte of the index

modifies H, then the user must stack and unstack H using the PSHH and

PULH instructions.

Bit

987654321

Bit 0

Read:

Write:

Reset:

Loaded with Vector from $FFFE and $FFFF

Figure 4-5. Program Counter (PC)

Bit 7

654321

Bit 0

Read:

Write:

Reset:

1X1X

X = Indeterminate

Figure 4-6. Condition Code Register (CCR)

M68HC08 Datasheet(PDF) 40 Page - Freescale Semiconductor, Inc

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