M68HC08 datasheet(91/172 Pages) FREESCALE

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Interrupts

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor

In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM

period.

In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width.

In TIM channel x status and control register (TSCx):

Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare

or PWM signals) to the mode select bits, MSxB:MSxA. (See Table 8-3.)

Write 1 to the toggle-on-overflow bit, TOVx.

Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level

select bits, ELSxB:ELSxA. The output action on compare must force the output to the

complement of the pulse width level. (See Table 8-3.)

NOTE

In PWM signal generation, do not program the PWM channel to toggle on

output compare. Toggling on output compare prevents reliable 0% duty

cycle generation and removes the ability of the channel to self-correct in the

event of software error or noise. Toggling on output compare can also

cause incorrect PWM signal generation when changing the PWM pulse

width to a new, much larger value.

In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.

Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel

0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSC0)

controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A.

Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output

compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle

output.

Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty

cycle output. (See 8.9.4 TIM Channel Status and Control Registers (TSC0:TSC1).)

8.5 Interrupts

The following TIM sources can generate interrupt requests:

•

TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value

programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE,

enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control

•

TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare

occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x

interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE=1.

CHxF and CHxIE are in the TIM channel x status and control register.

M68HC08 Datasheet(PDF) 91 Page - Freescale Semiconductor, Inc