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LP3918TL/NOPB Datasheet(PDF) 32 Page - Texas Instruments |
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LP3918TL/NOPB Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 38 page ![]() R/W S Slave Address (7 bits) '0' A A Control Register Add. (8 bits) From Slave to Master From Master to Slave Slave Address (7 bits) A Sr '1' R/W Data transferred, byte + Ack/NAck Register Data (8 bits) P A - ACKNOWLEDGE (SDA Low) S - START CONDITION P - STOP CONDITION NA - ACKNOWLEDGE (SDA High) Sr - REPEATED START CONDITION Direction of the transfer will change at this point NA A/ LP3918 SNVS476D – AUGUST 2007 – REVISED MAY 2013 www.ti.com Figure 18. Register Read Format 32 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP3918 |
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