PCM1602APT datasheet(20/46 Pages) TI2

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t(MCH)

1.4 V

t(MLS)

LSB

1.4 V

t(MCL)

t(MHH)

t(MLH)

t(MCY)

t(MDH)

t(MDS)

MDI

LSB

MDI

T0013-05

LSB

50% of VDD

MDO

t(MOS)

1.4 V

PCM1602A

SLES146A – AUGUST 2005 – REVISED OCTOBER 2010

www.ti.com

AUTO-INCREMENT READ OPERATION

The auto-increment read function allows for multiple registers to be read sequentially. The auto-increment read

function is enabled by setting the INC bit of control register 11 to 1. The sequence always starts with the register

indexed by the REG[6:0] bits in control register 11, and ends by the ML setting to 1 after MC clock cycle for the

least-significant bit of last register.

Figure 26 shows the timing of the auto-increment read operation. The operation begins by writing control register

11, setting INC to 1, and setting REG[6:0] to the first register to be read in the sequence. The actual read

operation starts on the next HIGH-to-LOW transition of the ML pin.

The read cycle starts by setting the R/W bit of the control word to 1, and setting all of the IDX[6:0] bits to 0. All

subsequent bits input on MDI are ignored while ML is set to 0. For the first eight clocks of the read cycle, MDO is

set to the high-impedance state. This is followed by a sequence of 8-bit words, each corresponding to the data

contained in control registers N through Y, where N is defined by the REG[6:0] bits in control register 11, and

where Y is the last register to be read. The read cycle is completed when ML is set to 1, immediately after the

MC clock cycle for the least-significant bit of the last register has completed. If ML is held low and the MC clock

continues beyond the last physical register (register 12), the read operation returns to control register 1 and

subsequent control registers, continuing until ML is set to 1.

CONTROL INTERFACE TIMING REQUIREMENTS

Figure 27 shows a detailed timing diagram for the serial control interface. Pay special attention to the setup and

hold times, as well as t(MLS) and t(MLH), which define minimum delays between the edges of the ML and MC

clocks. These timing parameters are critical for proper control-port operation.

SYMBOL

PARAMETER

MIN

MAX

UNITS

t(MCY)

MC pulse cycle time

100

t(MCL)

MC low-level time

t(MCH)

MC high-level time

t(MHH)

ML high-level time

300

t(MLS)

ML falling edge to MC rising edge

t(MLH)

ML hold time

t(MDH)

MDI hold time

t(MDS)

MDL setup time

t(MOS)

MC falling edge to MDO stable

(1)

MC rising edge for LSB to ML rising edge.

Figure 27. Control Interface Timing

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