S25FL256SDPNFVC datasheet(71/149 Pages) CYPRESS

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Document Number: 001-98283 Rev. *M

Page 70 of 148

S25FL128S/S25FL256S

9.1.3.2 Configuration

There are commands to read, write, and protect registers that control interface path width, interface timing, interface address length,

and some aspects of data protection.

9.1.4

Read Flash Array

Data may be read from the memory starting at any byte boundary. Data bytes are sequentially read from incrementally higher byte

addresses until the host ends the data transfer by driving CS# input High. If the byte address reaches the maximum address of the

memory array, the read will continue at address zero of the array.

There are several different read commands to specify different access latency and data path widths. Double Data Rate (DDR)

commands also define the address and data bit relationship to both SCK edges:



The Read command provides a single address bit per SCK rising edge on the SI signal with read data returning a single bit per

SCK falling edge on the SO signal. This command has zero latency between the address and the returning data but is limited to a

maximum SCK rate of 50 MHz.



Other read commands have a latency period between the address and returning data but can operate at higher SCK frequencies.

The latency depends on the configuration register latency code.



The Fast Read command provides a single address bit per SCK rising edge on the SI signal with read data returning a single bit

per SCK falling edge on the SO signal and may operate up to 133 MHz.



Dual or Quad Output read commands provide address a single bit per SCK rising edge on the SI / IO0 signal with read data

returning two bits, or four bits of data per SCK falling edge on the IO0-IO3 signals.



Dual or Quad I/O Read commands provide address two bits or four bits per SCK rising edge with read data returning two bits, or

four bits of data per SCK falling edge on the IO0-IO3 signals.



Fast (Single), Dual, or Quad Double Data Rate read commands provide address one bit, two bits or four bits per every SCK edge

with read data returning one bit, two bits, or four bits of data per every SCK edge on the IO0-IO3 signals. Double Data Rate (DDR)

operation is only supported for core and I/O voltages of 3 to 3.6V.

9.1.5

Program Flash Array

Programming data requires two commands: Write Enable (WREN), and Page Program (PP or QPP). The Page Program command

accepts from 1 byte up to 256 or 512 consecutive bytes of data (page) to be programmed in one operation. Programming means

that bits can either be left at 1, or programmed from 1 to 0. Changing bits from 0 to 1 requires an erase operation.

9.1.6

Erase Flash Array

The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array to 1. A bit needs to be

first erased to 1 before programming can change it to a 0. While bits can be individually programmed from a 1 to 0, erasing bits from

0 to 1 must be done on a sector-wide (SE) or array-wide (BE) level.

9.1.7

OTP, Block Protection, and Advanced Sector Protection

There are commands to read and program a separate One TIme Programmable (OTP) array for permanent data such as a serial

number. There are commands to control a contiguous group (block) of flash memory array sectors that are protected from program

and erase operations. There are commands to control which individual flash memory array sectors are protected from program and

erase operations.

9.1.8

Reset

There is a command to reset to the default conditions present after power on to the device. There is a command to reset (exit from)

the Enhanced Performance Read Modes.

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