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ELECTRICAL CHARACTERISTICS

PTH04070W

SLTS227B – SEPTEMBER 2004 – REVISED OCTOBER 2007

at 25C free-air temperature, VI = 5 V, VO = 3.3 V, IO = IO(Max), C1 = 47 μF, C2 = 47 μF (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IO

Output current

TA = 85°C, natural convection airflow

0

3

A

VI

Input voltage range

Over IO range

3

5.5

V

VO(tol)

Set-point voltage tolerance

TA = 25°C

±2 (1)

%VO

Temperature variation

-40

≤ TA ≤ +85°C

±0.5

%VO

Line regulation

Over VI range

±1

mV

Load regulation

Over IO range

±5

mV

Includes set-point, line, load,

Total output voltage variation

±3 (1)

%VO

–40

≤ TA ≤ +85°C

VI ≥ 4.5 V

0.9

3.6

VO(adj)

Output voltage adjust range

V

VI < 4.5 V

0.9

VI – 1.1

(2)

TA = 25°C, IO = 2 A

RSET = 475 Ω, VO = 3.3 V

(2)

92%

RSET = 2.32 kΩ, VO = 2.5 V V

(2)

90%

RSET = 4.87 kΩ, VO = 2 V

88%

η

Efficiency

RSET = 6.65 kΩ, VO = 1.8 V

87%

RSET = 11.5 kΩ, VO = 1.5 V

85%

RSET = 26.1 kΩ, VO = 1.2 V

82%

RSET = 84.5 kΩ, VO = 1 V

80%

Output voltage ripple

20 MHz bandwith

10

mVPP

IO(trip)

Overcurrent threshold

Reset, followed by autorecovery

7

A

C3 = 47

μF, 1 A/μs load step from 50% to

100% IOmax

Transient response

Recovery time

70

μs

VO over/undershoot

100

mV

VI = increasing

2.95

3

UVLO

Undervoltage lockout

V

VI = decreasing

2.7

2.8

Input high voltage (VIH)

VI – 0.5

Open (3)

V

Inhibit control (pin 5)

Input low voltage (VIL)

–0.2

0.6

Input low current (IIL)

–10

μA

II(stby)

Input standby current

Pin 5 connected to GND

1

mA

FS

Switching frequency

Over VI and IO ranges

700

kHz

External input capacitance

Ceramic type (C1)

47 (4)

μF

Ceramic type (C2)

47 (5)

200

μF

External output capacitance

Nonceramic type (C3)

47 (5)

560 (6)

Equivalent series resistance (nonceramic)

4 (7)

m

Ω

Per Bellcore TR-332, 50% stress,

MTBF

Calculated reliability

48

106 Hrs

TA = 40°C, ground benign

(1)

The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a

tolerance of 1% with with 100 ppm/

°C or better temperature stability.

(2)

The minimum input voltage is 3 V or (VO + 1.1) V, whichever is greater. A 5-V input bus is recommended for output voltages higher than

2 V.

(3)

This control pin has an internal pullup to the input voltage VI. If it is left open circuit, the module operates when input power is applied. A

small low-leakage (<100 nA) MOSFET is recommended for control. Do not tie the inhibit pin to VI or to another module's inhibit pin. See

the application section for further guidance.

(4)

An external 47-

μF ceramic capacitor is required across the input (VI and GND) for proper operation. Locate the capacitor close to the

module.

(5)

An external 47-

μF ceramic capacitor is required across the output (VO and GND) for proper operation. Locate the capacitor close to the

module. Adding another 47

μF of electrolytic capacitance close to the load improves the response of the regulator to load transients.

(6)

This is the calculated maximum capacitance. The minimum ESR limitation often results in a lower value. See the capacitor application

information for further guidance.

(7)

This is the typical ESR for all the electrolytic (nonceramic) capacitance. Use 7 m

Ω as the minimum when calculating the total equivalent

series resistance (ESR) using the max-ESR values specified by the capacitor manufacturer.

Copyright © 2004–2007, Texas Instruments Incorporated

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