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AM53C96KC Datasheet(PDF) 22 Page - Advanced Micro Devices

Part # AM53C96KC
Description  High Performance SCSI Controller
PDF  63 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM53C96KC Datasheet(HTML) 22 Page - Advanced Micro Devices

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P R E L I M I N A R Y
AMD
22
Am53C94/Am53C96
SCSI Timeout Register (05H) Write
SCSI Timeout Register
STIMREG
Address: 05H
Type: Write
76543
210
STIM7
STIM6
STIM5
STIM4
STIM3
STIM2
STIM1
STIM0
xxxxx
xxx
16506C-23
This register determines how long the initiator (target)
will wait for a target to respond to a selection (reselec-
tion) before timing out. It should be set to yield 250 ms to
comply with ANSI standards for SCSI.
STIMREG – Bits 7:0 – STIM 7:0 – SCSI Timer 7:0
The value loaded in STIM 7:0 can be calculated from the
following formula:
STIM 7:0 =
[(SCSI Time Out) (Clock Frequency) / (8192 (Clock
Factor))]
Example:
SCSI Time Out (in seconds): 250 ms. (Recommended
by the ANSI Standard) = 250 x 10–3 s.
Clock Frequency: 20 MHz. (assume) = 20 x 106 Hz.
Clock Factor: CLKF 2:0 from Clock Conversion Regis-
ter (09H) = 5
STIM 7:0 = (250 x 10–3) X (20 x 106) / (8192 (5)) = 122
decimal
Internal State Register (06H) Read
Internal State Register
ISREG
Address: 06H
Type: Read
76543
210
RES
RES
RES
RES
SOF
IS2
IS1
IS0
xxxx
0
0
0
0
Reserved
Reserved
Reserved
Synchronous Offset Flag
Internal State 2:0
Reserved
16506C-24
The Internal State Register (ISREG) tracks the progress
of a sequence-type command. It is updated after each
successful completion of an intermediate operation. If
an error occurs, the host can read this register to deter-
mined at where the command failed and take the neces-
sary procedure for recovery. Reading the Interrupt
Status Register will clear this register.
ISREG – Bits 7:4 – RES – Reserved
ISREG – Bit 3 – SOF – Synchronous Offset Flag
The SOF is reset when the Synchronous Offset Register
(SOFREG) has reached its maximum value.
Note:
The SOF bit is active Low.
ISREG – Bits 2:0 – IS 2:0 – Internal State 2:0
The IS 2:0 bits along with the Interrupt Status Register
(INSTREG) indicates the status of the successfully
completed intermediate operation. Refer to the Status
Decode section for more details.



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