ISL85003, ISL85003A

FN7968 Rev.3.02

Page 4 of 23

Apr 15, 2024

Pin Configurations

ISL85003

(12 ld 3X4 DFN)

TOP VIEW

ISL85003A

(12 LD 3X4 DFN)

TOP VIEW

SYNC

PG

EN

FB

COMP

BOOT

VDD

VIN

VIN

PHASE

AGND

2

3

4

1

5

11

10

9

12

8

6

7 PHASE

PGND

13

SS

PG

EN

FB

COMP

BOOT

VDD

VIN

VIN

PHASE

AGND

2

3

4

1

5

11

10

9

12

8

6

7 PHASE

PGND

13

Pin Descriptions

PIN

NUMBER

PIN

NAME

DESCRIPTION

1

(ISL85003)

SYNC

Synchronization and mode selection input. Connect to VDD for CCM mode. Connect to AGND for DCM mode. Connect to an

external function generator for synchronization with the positive edge trigger. There is an internal 1MΩ pull-up resistor to VDD,

which prevents an undefined logic state in cases where SYNC is floating.

1

(ISL85003A)

SS

Soft-Start input. This pin provides a programmable soft-start. When the chip is enabled, the regulated 4µA pull-up current

source charges a capacitor connected from SS to ground. The output voltage of the converter follows the ramping voltage on

this pin. Without the external capacitor, the default soft-start is 2ms.

2

PG

Power-good open-drain output. Connect 10kΩ to 100kΩ pull-up resistor between PG and VDD or between PG and a voltage not

exceeding 5.5V. PG transitions high about 1ms after the switching regulator’s output voltage reaches the regulation threshold,

which is 85% of the regulated output voltage typically.

3

EN

Enable input. The regulator is held off when the pin is pulled to ground. The device is enabled when the voltage on this pin rises

above 0.6V.

4

FB

Feedback input. The synchronous buck regulator employs a current mode control loop. FB is the negative input to the voltage

loop error amplifier. The output voltage is set by an external resistor divider connected to FB. The output voltage can be set to

any voltage between the power rail (reduced by converter losses) and the 0.8V reference.

5

COMP

Compensation node. This pin is connected to the output of the error amplifier, and is used to compensate the loop. Internal

compensation is used to meet most applications. Connect COMP to AGND to select internal compensation. Connect a

compensation network between COMP and FB to use external compensation.

6

AGND

The AGND terminal provides the return path for the core analog control circuitry within the device. Connect AGND to the board

ground plane. AGND and PGND are connected internally within the device. Do not operate the device with AGND and PGND

connected to dissimilar voltages.

7, 8

PHASE Phase switch output node. This is the main output of the device. Connect to the external output inductor.

9, 10

VIN

Voltage supply input. The main power input for the IC. Connect to a suitable voltage supply. Place a ceramic capacitor from VIN

to PGND, close to the IC for decoupling (typical 10µF).

11

VDD

Low dropout linear regulator decoupling pin. VDD is the internally generated 5V supply voltage and is derived from VIN. The

VDD is used to power all the internal core analog control blocks and drivers. Connect a 1µF capacitor from VDD to the board

ground plane. If VIN is between 4.5V to 5.5V, then connect VDD directly to VIN to improve efficiency.

12

BOOT

Bootstrap input. Floating bootstrap supply pin for the upper power MOSFET gate driver. Connect a 0.1µF capacitor between

BOOT and PHASE.

13

(EPAD)

PGND

Power ground terminal. Provides thermal relief for the package and is connected to the source of the low-side output MOSFET.

Connect PGND to the board ground plane using as many vias as possible. AGND and PGND are connected internally within the

device. Do not operate the device with AGND and PGND connected to dissimilar voltages.