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TLC320AD50C/I Datasheet(PDF) 41 Page - Texas Instruments |
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TLC320AD50C/I Datasheet(HTML) 41 Page - Texas Instruments |
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41 / 54 page  5–2 twH twL td1 td2 ten1 tsu1 th1 tdis1 MCLK SCLK FS DOUT DIN D15 D14 D15 D14 NOTE A: The master mode and D0 through D5 of control 3 register are greater than 17. Figure 5–4. Serial Communication Timing (Master Mode) tsu2 D15 D14 D15 D14 twH twL td4 td5 ten2 tdis2 th2 MCLK SCLK FS DOUT DIN Figure 5–5. Serial Communication Timing (Slave Mode) |
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