PIC16F570 datasheet(43/129 Pages) MICROCHIP

43 / 129 page

 2013-2014 Microchip Technology Inc.

DS40001684E-page 43

PIC16F570

8.4.1

MCLR ENABLE

This Master Clear (MCLR) feature and its associated

pull-up are always enabled on this device. The pin is

assigned to be an input-only pin function.

FIGURE 8-6:

MCLR INPUT PIN

8.5

Power-on Reset (POR)

The PIC16F570 device incorporates an on-chip Power-

on Reset (POR) circuitry, which provides an internal

chip Reset for most power-up situations.

The on-chip POR circuit holds the chip in Reset until

VDD has reached a high enough level for proper

operation. To take advantage of the internal POR, an

internal weak pull-up resistor is implemented using a

transistor (refer to Table 15-11 for the pull-up resistor

ranges). This will eliminate external RC components

usually needed to create a Power-on Reset. A

maximum rise time for VDD is specified. See

Section 15.0 “Electrical Characteristics” for details.

When the device starts normal operation (exit the

Reset

condition),

device

operating

parameters

(voltage, frequency, temperature,...) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

parameters are met.

A simplified block diagram of the on-chip Power-on

Reset circuit is shown in Figure 8-7.

The Power-on Reset circuit and the Device Reset

Timer (see Section 8.6 “Device Reset Timer (DRT)”)

circuit are closely related. On Power-up, the Reset

latch is set and the DRT is reset. The DRT timer begins

counting once it detects MCLR to be high. After the

time-out period, it will reset the Reset latch and thus

end the on-chip Reset signal.

A Power-up example where MCLR is held low is shown

in Figure 8-8. VDD is allowed to rise and stabilize before

bringing MCLR high. The chip will actually come out of

Reset TDRT ms after MCLR goes high.

In Figure 8-9, the on-chip Power-on Reset feature is

being used (MCLR is tied to VDD or pulled high by its

internal pull-up). The VDD is stable before the start-up

timer times out and there is no problem in getting a

proper Reset. However, Figure 8-10 depicts a problem

situation where VDD rises too slowly. The time between

when the DRT senses that MCLR is high and when

MCLR and VDD actually reach their full value, is too

long. In this situation, when the start-up timer times out,

VDD has not reached the VDD (min) value and the chip

may not function correctly. For such situations, we

recommend that external RC circuits be used to

achieve longer POR delay times (Figure 8-9).

For additional information, refer to Application Notes

AN522, “Power-Up Considerations” (DS00522) and

AN607, “Power-up Trouble Shooting” (DS00607).

MCLR/VPP

Internal MCLR

Note:

When the device starts normal operation

(exit the Reset condition), device operat-

ing parameters (voltage, frequency, tem-

perature, etc.) must be met to ensure

operation. If these conditions are not met,

the device must be held in Reset until the

operating conditions are met.

PIC16F570 Datasheet(PDF) 43 Page - Microchip Technology

PIC16F570 Datasheet(HTML) 43 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL