TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

3

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

detailed description

analog-to-digital converter

The TLV1570 ADC uses the SAR architecture described in this section. The CMOS threshold detector in the

successive-approximation conversion system determines the value of each bit by examining the charge on a

series of binary-weighted capacitors (see Figure 1). In the first phase of the conversion process, the analog input

is sampled by closing the SC switch and all ST switches simultaneously. This action charges all of the capacitors

to the input voltage.

SC

Threshold

Detector

Node 512

REF –

REF+

ST

512

VI

To Output

Latches

REF –

ST

REF+

REF –

ST

REF+

REF –

ST

REF+

REF –

ST

REF+

ST

REF+

REF –

ST

REF+

REF –

ST

1

1

2

4

8

128

256

REF –

NOTE: REF– is tied to AGND

Figure 1. Simplified Model of the Successive-Approximation System

In the next phase of the conversion process, all ST and SC switches are opened and the threshold detector

begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF–)

voltage (REF– is tied to AGND). In the switching sequence, ten capacitors are examined separately until all ten

bits are identified and then the charge-convert sequence is repeated. In the first step of the conversion phase,

the threshold detector looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the

REF+ voltage, and the equivalent nodes of all the other capacitors on the ladder are switched to REF–. If the

voltage at the summing node is greater than the trip point of the threshold detector (approximately one-half VCC),

a bit 0 is placed in the output register and the 512-weight capacitor is switched to REF–. If the voltage at the

summing node is less than the trip point of the threshold detector, a bit 1 is placed in the register and the

512-weight capacitor remains connected to REF+ through the remainder of the successive-approximation

process. The process is repeated for the 256-weight capacitor, the 128-weight capacitor, and so forth down the

line until all bits are counted.

With each step of the successive-approximation process, the initial charge is redistributed among the

capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.

In the case of the TLV1570, REF– is tied to ground and REF+ is connected to the REF input.

The TLV1570 can be programmed to use the on-chip internal reference (DI6=1). The user can select between

two values of internal reference, 2.3 V or 3.8 V, using the control bit DI5.

During internal reference mode, the reference voltage is not output on the REF pin. Therefore it cannot be

decoupled to analog ground (AGND), which acts as the negative reference for the ADC, using an external

capacitor. Hence this mode requires the ground noise to be very low. The REF pin can be left open in this mode.