TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

9

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

simplified analog input analysis

Using the equivalent circuit in Figure 6, the time required to charge the analog input capacitance from 0 to VS

within 1/2 LSB, tch(1/2 LSB), can be derived as follows:

The capacitance charging voltage is given by:

Where:

Rt = Rs + Ri

Ri = Ri(ADC) + Ri(MUX)

tch = Charge time

V

C(t) +

V

S

1–e

–t

ch

RtCi

The input impedance Ri is 718 Ω at 5 V, and is higher (~1.25 kΩ) at 2.7 V. The final voltage to 1/2 LSB is given

by:

VC (1/2 LSB) = VS – (VS/2048)

Equating equation 1 to equation 2 and solving for cycle time tc gives:

and time to change to 1/2 LSB (minimum sampling time) is:

tch (1/2 LSB) = Rt × Ci × ln(2048)

V

S *

V

S

2048

+ V

S

1–e

–t

ch

RtCi

Where:

ln(2048) = 7.625

Therefore, with the values given, the time for the analog input signal to settle is:

tch (1/2 LSB) = (Rs + 718 Ω) × 15 pF × ln(2048)

This time must be less than the converter sample time shown in the timing diagrams. Which is 6x SCLK.

tch (1/2 LSB) ≤ 6x 1/f(SCLK)

Therefore the maximum SCLK frequency is:

Max(f(SCLK)) = 6/tch (1/2 LSB) = 6/(ln(2048) × Rt × Ci)

Rs

Ri(MUX)

VS

VC

15 pF

Driving Source†

TLC1570

Ci

VI

VI = Input Voltage at AIN

VS = External Driving Source Voltage

Rs = Source Resistance

Ri(ADC)= Input Resistance of ADC

Ri(MUX)= Input Resistance (MUX on resistance)

Ci = Input Capacitance

VC= Capacitance Charging Voltage

† Driving source requirements:

• Noise and distortion for the source must be equivalent to the resolution of the converter.

• Rs must be real at the input frequency.

Ri(ADC)

MO

AIN

Figure 6. Equivalent Input Circuit Including the Driving Source

(1)

(2)

(3)

(4)

(5)

(6)