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PARALLEL INTERFACE

Address

Decoder

A(0–15)

IS

WE

D(0–15)

CS

LDAC

WE

D(0–11)

TMS320C2XX, 5X

TLV5619

Address

Decoder

A(0–15)

TCLK0

R/W

D(0–15)

CS

LDAC

WE

D(0–11)

TMS320C3X

TLV5619

IOSTROBE

TLV5619

SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004

APPLICATION INFORMATION (continued)

The device latches data on the positive edge of WE. It must be enabled with CS low. LDAC low updates the

DAC with the value in the holding latch. LDAC is an asynchronous input and can be held low, if a separate

update is not necessary. However, to control the DAC using the load feature, LDAC can be driven low after the

positive WE edge.

Figure 11. Proposed Interface Between TLV5619 and TMS320C2XX, 5X DSPs

Figure 12. Proposed Interface Between TLV5619 and TMS320C3X DSPs

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