TB026

DS91026A-page 2

© 1998 Microchip Technology Inc.

FIGURE 1:

EECON1 REGISTER

R/W-x

U-0

U-0

U-0

R/W-x

R/W-0

R/S-0

R/S-0

EEPGD

—

—

—

WRERR

WREN

WR

RD

R

= Readable bit

W = Writable bit

S

= Settable bit

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7:

EEPGD: Program / Data EEPROM Select bit

1 = Accesses Program memory

0 = Accesses data memory

Note: This bit cannot be changed while a write operation is in progress.

bit 6:4:

Unimplemented: Read as '0'

bit 3:

WRERR: EEPROM Error Flag bit

1 = A write operation is prematurely terminated

(any MCLR reset or any WDT reset during normal operation)

0 = The write operation completed

bit 2:

WREN: EEPROM Write Enable bit

1 = Allows write cycles

0 = Inhibits write to the EEPROM

bit 1:

WR: Write Control bit

1 = initiates a write cycle. (The bit is cleared by hardware once write is complete.

The WR bit can only be set (not cleared) in software.

0 = Write cycle to the EEPROM is complete

bit 0:

RD: Read Control bit

1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware.

The RD bit can only be set (not cleared) in software).

0 = Does not initiate an EEPROM read