TC3097-8
Preliminary Data Sheet
(its /ACKI input is tied high), then the /ACKO signal from this LEMRIC is send to the /ACKI input of the
next LEMRIC and so on. This arrangement is simple to implement but it places some topological
restrictions upon the repeater system. In particular, when the repeater is constructed using a backplane
with removable printed circuit boards containing the LEMRICs, If one of the boards is removed then the
/ACKI-/ACKO chain will be broken and the repeater will not operate correctly.
The second method of PORT N or PORT M identification avoids this problem. This second technique
relies on an external parallel arbiter, which monitors all of the LEMRIC's /ACKO signals and responds to
the LEMRIC with the highest priority. In this scheme each LEMRIC is assigned with a priority level. One
method of doing this is to assign a priority number, which reflects the position of a LEMRIC board on the
repeater backplane (i.e., its slot number). When a LEMRIC experiences receive activity and the repeater
system is in the IDLE state, the LEMRIC board will assert /ACKO. External arbitration logic drives the
identification number onto an arbitration bus and the LEMRIC containing PORT N will be identified. An
identical procedure is used in the TRANSMIT COLLISION state to identify PORT M. This parallel means
of arbitration is not subject to the problems caused by missing boards (I. e., empty slots in the backplane).
The logic associated with asserting this arbitration vector in the various in the various packet repetition
scenarios could be implemented in PAL or GAL type devices.
To perform PORT N or PORT M arbitration, both of the above methods employ the same signals: /ACKI,
/ACKO, and /ACTN.
The Inter-LEMRIC bus allows multi-LEMRIC operations to be performed in exactly the same manner as
if there is only a single LEMRIC in the system. The simplest way to describe the operation of
Inter-LEMRIC bus is to see how it is used in a number of common packet repetition scenarios.
2.3.6.2 EXAMPLES OF PACKET REPETITION SCENARIOS
Data Repetition
The simplest packet operation performed over the Inter-LEMRIC Bus is data repetition. In this operation
a data packet is received at one port and transmitted to all other segments.
The first task to be performed is PORT N identification. In situations where two or more ports
simultaneously receive packets the Inter-LEMRIC bus operates by choosing one of the active ports and
forcing the others to transmit data. This is done to faithfully follow the IEEE specification's allowed exit
paths from the IDLE state (I. e., to the SEND PREAMBLE PATTERN or RECEIVE COLLISION states).
The packet begins with a preamble pattern derived from the LEMRIC's on chip jam/preamble generator.
The data received at PORT N is directed through the receiving multiplexer to the PLL decoder. Once
phase lock has been achieved, the decoded data, in NRZ format, with its associated clock and enable
signals are asserted onto to IRD, /IRE and IRC Inter-LEMRIC bus lines, This serial data stream is
received from the bus by all LEMRICs in the repeater and directed to their Elasticity Buffers. Logic circuit
monitors the data stream and look for the Start of Frame Delimiter (SFD).
When this has been detected data is loaded into the elasticity buffer for later transmission. This will occur
when sufficient preamble has been transmitted and certain internal state machine operations have been
fulfilled.
Figure 11 shows two LEMRICs, A and B, daisy-chained together with LEMRIC A positioned at the top of
the chain. A packet is received at port B1 of LEMRIC B and is then repeated by the other ports in the
system. Figure 12 shows the functional timing diagram for this packet repetition represented by the
signals shown in figure 11. In this example only two ports in the system are shown, obviously the other
port also repeat the packet. It also indicates the operation of the LEMRIC's state machines in so far as
can be seen by observing the Inter-LEMRIC bus. For reference, the repeater's state transitions are
shown in terms of the states defined by the IEEE specification. The location (I. e., which port it is) of
Confidential.
21/35
July 21. 2003
Copyright © 2003, IC Plus Corp.
TC3097-8-DS-R24
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
