ADS5424IPGPR.B datasheet(20/29 Pages) TI2

20 / 29 page

ADS5424

SLWS157B − JANUARY 2005 − REVISED JANUARY 2010

www.ti.com

APPLICATION INFORMATION

Figure 44 shows this approach. The back-to-back

Schottky can be added to limit the clock amplitude in

cases where this would exceed the absolute maximum

ratings, even when using a differential clock. Figure 22

and Figure 23 show the performance versus input clock

amplitude for a sinusoidal clock.

CLK

ADS5424

CLK

VBB

MC100EP16DT

Ω

100 nF

Ω

113

Ω

100 nF

499

Figure 45. Differential Clock Using PECL Logic

Another possibility is the use of a logic based clock, as

PECL. In this case, the slew rate of the edges will most

likely be much higher than the one obtained for the

same clock amplitude based on a sinusoidal clock. This

solution would minimize the effect of the slope

dependent ADC jitter. Nevertheless, observe that for

the ADS5424, this term is small and has been

optimized. Using logic gates to square a sinusoidal

clock may not produce the best results as logic gates

may not have been optimized to act as comparators,

adding too much jitter while squaring the inputs.

The common-mode voltage of the clock inputs is set

internally to 2.4 V using internal 1 k

Ω resistors. It is

recommended to use an ac coupling, but if for any

reason, this scheme is not possible, due to, for

instance,

asynchronous

clocking,

the

ADS5424

presents a good tolerance to clock common-mode

variation (see Figure 20).

Additionally, the internal ADC core uses both edges of

the clock for the conversion process. This means that,

ideally, a 50% duty cycle should be provided. Figure 21

shows the performance variation of the ADC versus

clock duty cycle.

DIGITAL OUTPUTS

The ADC provides 14 data outputs (D13 to D0, with D13

being the MSB and D0 the LSB), a data-ready signal

(DRY, pin 52), and an out-of-range indicator (OVR, pin

32) that equals 1 when the output reaches the full-scale

limits.

The output format is two’s complement. When the input

voltage is at negative full scale (around −1.1 V

differential), the output will be, from MSB to LSB, 10

0000 0000 0000. Then, as the input voltage is

increased, the output switches to 10 0000 0000 0001,

10 0000 0000 0010 and so on until 11 1111 1111 1111

right before mid-scale (when both inputs are tight

together if we neglect offset errors). Further increases

on input voltage, outputs the word 00 0000 0000 0000,

to be followed by 00 0000 0000 0001, 00 0000 0000

0010 and so on until reaching 01 1111 1111 1111 at

full-scale input (1.1-V differential).

Although the output circuitry of the ADS5424 has been

designed to minimize the noise produced by the

transients of the data switching, care must be taken

when designing the circuitry reading the ADS5424

outputs. Output load capacitance should be minimized

by minimizing the load on the output traces, reducing

their length and the number of gates connected to them,

and by the use of a series resistor with each pin. Typical

numbers on the data sheet tables and graphs are

obtained with 100

Ω series resistor on each digital

output pin, followed by a 74AVC16244 digital buffer as

the one used in the evaluation board.

POWER SUPPLIES

The use of low noise power supplies with adequate

decoupling is recommended, being the linear supplies

the first choice versus switched ones, which tend to

generate more noise components that can be coupled

to the ADS5424.

ADS5424IPGPR.B Datasheet(PDF) 20 Page - Texas Instruments

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