CD74HC40103EP

HIGHSPEED CMOS LOGIC

8STAGE SYNCHRONOUS DOWN COUNTER

SCLS548 − DECEMBER 2003

1

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

D Controlled Baseline

− One Assembly/Test Site, One Fabrication

Site

D Extended Temperature Performance of

−40

°C to 125°C

D Enhanced Diminishing Manufacturing

Sources (DMS) Support

D Enhanced Product-Change Notification

D Qualification Pedigree†

D Synchronous or Asynchronous Preset

D Cascadable in Synchronous or Ripple

Mode

D Fanout (Over Temperature Range)

− Standard Outputs ... 10 LSTTL Loads

− Bus Driver Outputs ... 15 LSTTL Loads

† Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

D Balanced Propagation Delay and Transition

Times

D Significant Power Reduction Compared to

LSTTL Logic ICs

D VCC Voltage = 2 V to 6 V

D High Noise Immunity NIL or NIH = 30% of

VCC, VCC = 5 V

description/ordering information

The CD74HC40103 is manufactured with high-speed silicon-gate technology and consists of an 8-stage

synchronous down counter with a single output, which is active when the internal count is zero. The device

contains a single 8-bit binary counter. Each device has control inputs for enabling or disabling the clock, for

clearing the counter to its maximum count, and for presetting the counter either synchronously or

asynchronously. All control inputs and the terminal count (TC) output are active-low logic.

In normal operation, the counter is decremented by one count on each positive transition of the clock (CP)

output. Counting is inhibited when the terminal enable (TE) input is high. TC goes low when the count reaches

zero, if TE is low, and remains low for one full clock period.

When the synchronous preset enable (PE) input is low, data at the P0−P7 inputs are clocked into the counter on

the next positive clock transition, regardless of the state of TE. When the asynchronous preset enable (PL) input

is low, data at the P0−P7 inputs asynchronously are forced into the counter, regardless of the state of the PE, TE,

or CP inputs. Inputs P0−P7 represent a single 8-bit binary word for the CD74HC40103. When the master reset

(MR) input is low, the counter asynchronously is cleared to its maximum count of 25510, regardless of the state of

any other input. The precedence relationship between control inputs is indicated in the truth table.

ORDERING INFORMATION

TA

PACKAGE‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−40

°C to 125°C

SOIC − M

Tape and reel

CD74HC40103QM96EP

HC40103QEP

‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Copyright

 2003, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

M PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

CP

MR

TE

P0

P1

P2

P3

GND

VCC

PE (SYNC)

TC

P7

P6

P5

P4

PL (ASYNC)