TSC2102IDA.A datasheet(22/58 Pages) TI2

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TSC2102

SLAS379A− APRIL 2003 − REVISED JUNE 2004

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OPERATION− STEREO AUDIO DAC

Audio Analog I/O

The TSC2102 has one stereo headphone output capable of driving a 16-

Ω load at over 25 mW (with 3.3-V supply) (HPR,

HPL). The headphone driver can be bypassed by setting D12 in the control register 05H/Page2 to 0. The TSC2102 also

has a virtual ground (VGND) output, which can be optionally used to connect to the ground terminal of headphones to

eliminate the ac-coupling capacitor at the headphone output terminal. Bit D8 of control register 05H/Page2 controls the

VGND amplifier. A special circuit has been included in the TSC2102 to insert a short keyclick sound into the stereo audio

output, even when the audio DAC is powered down. The keyclick sound is used to provide feedback to the user when a

particular button is pressed or item is selected. The specific sound of the keyclick can be adjusted by varying several

Digital Audio Interface

Digital audio data samples can be transmitted between the TSC2102 and the CPU via the audio data serial port (BCLK,

LRCK, DIN) that can be configured to transfer digital data in four different formats: right justified, left justified, I2S, and DSP.

The four modes are MSB first and operate with variable word length of 16/20/24/32 bits. The TSC2102 audio data serial

port can operate in master or slave mode. The word-select signal (LRCK) and bit clock signal (BCLK) are output in master

mode and input in slave mode, and both can be turned off by software power down. The LRCK also is the synchronization

signal for DIN and represents the sampling rate of the DAC. All registers, including those pertaining to audio functionality,

are only configured via the SPI bus.

D DAC SAMPLING RATE

The audio-control-1 register (Register 00H, Page 2) determines the sampling rates of DAC, which is scaled down from

the reference rate (Fsref) of either 44.1 kHz or 48 kHz, which is selectable by bit D13 of control register 06H/Page2. The

frequency of the LRCK represents the sampling rate of the DAC. At power up, it is configured as an I2S SLAVE with the

DAC operating at Fsref.

D WORD SELECT SIGNALS

The word select signal (LRCK) indicates the channel being transmitted:

−

LRCK = 0: left channel for I2S mode

−

LRCK = 1: right channel for I2S mode

For other modes, check the timing diagrams below.

D 256−S TRANSFER MODE

In the 256-S mode, the BCLK rate always equals 256 times the LRCK frequency. In the 256-S transfer mode, the

combination of the 48-ksps sampling rate and left-justified mode is not supported.

D CONTINUOUS TRANSFER MODE

In continuous transfer mode, the BCLK rate always equals two times the word length times the LRCK frequency.

D RIGHT-JUSTIFIED MODE

In right-justified mode, the LSB of the left channel is valid on the rising edge of the BCLK preceding the falling edge of

LRCK. Similarly, the LSB of the right channel is valid on the rising edge of the BCLK preceding the rising edge of LRCK.

BCLK

LRCK

DIN

n−1

1/fs

LSB

MSB

Left Channel

Right Channel

n−2

Figure 18. Timing Diagram for Right-Justified Mode

TSC2102IDA.A Datasheet(PDF) 22 Page - Texas Instruments

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