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TSC2102IDA.A Datasheet(PDF) 7 Page - Texas Instruments |
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TSC2102IDA.A Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 58 page ![]() TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 www.ti.com 7 SPI TIMING DIAGRAM t td ta tsck t Lead t Lag t wsck t wsck t r t f t v t h o t dis t hi tsu SS SCLK MISO MOSI MSB IN BIT 6 . . . 1 LSB OUT BIT 6 . . . 1 LSB IN MSB OUT TYPICAL TIMING REQUIREMENTS All specifications at 25 °C, IOVDD = 3.3 V, DVDD = 1.8 V(1) PARAMETER MIN MAX UNITS twsck SCLK pulse width 18 ns tLead Enable lead time 15 ns tLag Enable lag time 15 ns ttd Sequential transfer delay 15 ns ta Slave MISO access time 15 ns tdis Slave MISO disable time 15 ns tsu MOSI data setup time 6 ns thi MOSI data hold time 6 ns tho MISO data hold time 4 ns tv MISO data valid time 13 ns tr Rise time 4 ns tf Fall time 4 ns (1) These parameters are based on characterization and are not tested in production. |
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